summaryrefslogtreecommitdiff
path: root/src/mem/packet.hh
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2015-07-03 10:14:41 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-07-03 10:14:41 -0400
commit71856cfbbcac94997839ac7831b3ac4b2ddf29a2 (patch)
treef4f6a3af3efca446c09b0c8898649d5622f649eb /src/mem/packet.hh
parent0ddde83a47e8a129de1a5c00475772c6ac0fd004 (diff)
downloadgem5-71856cfbbcac94997839ac7831b3ac4b2ddf29a2.tar.xz
mem: Split WriteInvalidateReq into write and invalidate
WriteInvalidateReq ensures that a whole-line write does not incur the cost of first doing a read exclusive, only to later overwrite the data. This patch splits the existing WriteInvalidateReq into a WriteLineReq, which is done locally, and an InvalidateReq that is sent out throughout the memory system. The WriteLineReq re-uses the normal WriteResp. The change allows us to better express the difference between the cache that is performing the write, and the ones that are merely invalidating. As a consequence, we no longer have to rely on the isTopLevel flag. Moreover, the actual memory in the system does not see the intitial write, only the writeback. We were marking the written line as dirty already, so there is really no need to also push the write all the way to the memory. The overall flow of the write-invalidate operation remains the same, i.e. the operation is only carried out once the response for the invalidate comes back. This patch adds the InvalidateResp for this very reason.
Diffstat (limited to 'src/mem/packet.hh')
-rw-r--r--src/mem/packet.hh9
1 files changed, 3 insertions, 6 deletions
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 49a50125e..54f2176c6 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -92,8 +92,7 @@ class MemCmd
HardPFReq,
SoftPFResp,
HardPFResp,
- WriteInvalidateReq,
- WriteInvalidateResp,
+ WriteLineReq,
UpgradeReq,
SCUpgradeReq, // Special "weak" upgrade for StoreCond
UpgradeResp,
@@ -122,7 +121,8 @@ class MemCmd
// Fake simulator-only commands
PrintReq, // Print state matching address
FlushReq, //request for a cache flush
- InvalidationReq, // request for address to be invalidated from lsq
+ InvalidateReq, // request for address to be invalidated
+ InvalidateResp,
NUM_MEM_CMDS
};
@@ -188,8 +188,6 @@ class MemCmd
bool needsExclusive() const { return testCmdAttrib(NeedsExclusive); }
bool needsResponse() const { return testCmdAttrib(NeedsResponse); }
bool isInvalidate() const { return testCmdAttrib(IsInvalidate); }
- bool isWriteInvalidate() const { return testCmdAttrib(IsWrite) &&
- testCmdAttrib(IsInvalidate); }
/**
* Check if this particular packet type carries payload data. Note
@@ -483,7 +481,6 @@ class Packet : public Printable
bool needsExclusive() const { return cmd.needsExclusive(); }
bool needsResponse() const { return cmd.needsResponse(); }
bool isInvalidate() const { return cmd.isInvalidate(); }
- bool isWriteInvalidate() const { return cmd.isWriteInvalidate(); }
bool hasData() const { return cmd.hasData(); }
bool isLLSC() const { return cmd.isLLSC(); }
bool isError() const { return cmd.isError(); }