rename store conditional stuff as extra data so it can be used for conditional swaps as well

Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic

src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
    rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
    add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
    Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
    Make atomic memory ops atomic
    Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
    add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
    remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
    swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
    add a post access code block
src/arch/sparc/isa/includes.isa:
    need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
    add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
    add support for twinloads
    add support for swap and conditional swap instructions
    rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
    Add support for atomic swap memory commands
src/mem/packet_access.hh:
    Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
    Add support for atomic swap memory commands
    Rename sc code to extradata

--HG--
extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656

1 files changed, 5 insertions, 0 deletions

diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 65d2207db..16410594a 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -88,6 +88,8 @@ class MemCmd
         UpgradeReq,
         ReadExReq,
         ReadExResp,
+        SwapReq,
+        SwapResp,
         NUM_MEM_CMDS
     };
 
@@ -106,6 +108,7 @@ class MemCmd
         IsHWPrefetch,
         IsUpgrade,
         HasData,
+        IsReadWrite,
         NUM_COMMAND_ATTRIBUTES
     };
 
@@ -141,6 +144,7 @@ class MemCmd
     bool needsResponse() const  { return testCmdAttrib(NeedsResponse); }
     bool isInvalidate() const   { return testCmdAttrib(IsInvalidate); }
     bool hasData() const        { return testCmdAttrib(HasData); }
+    bool isReadWrite() const    { return testCmdAttrib(IsReadWrite); }
 
     const Command responseCommand() const {
         return commandInfo[cmd].response;
@@ -300,6 +304,7 @@ class Packet
     bool needsResponse() const  { return cmd.needsResponse(); }
     bool isInvalidate() const   { return cmd.isInvalidate(); }
     bool hasData() const        { return cmd.hasData(); }
+    bool isReadWrite() const    { return cmd.isReadWrite(); }
 
     bool isCacheFill() const    { return (flags & CACHE_LINE_FILL) != 0; }
     bool isNoAllocate() const   { return (flags & NO_ALLOCATE) != 0; }