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authorAnthony Gutierrez <atgutier@umich.edu>2012-08-15 10:38:08 -0400
committerAnthony Gutierrez <atgutier@umich.edu>2012-08-15 10:38:08 -0400
commit0b3897fc90901953e9d016466c37ab507f85023c (patch)
tree0e8b1fec8d7c4871686903d573e9fd0fd8734d1e /src/mem/packet_queue.cc
parent5a648f2074caad8aee97e03f27e8eecc527a2cba (diff)
downloadgem5-0b3897fc90901953e9d016466c37ab507f85023c.tar.xz
O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
This patch fixes some problems with the drain/switchout functionality for the O3 cpu and for the ARM ISA and adds some useful debug print statements. This is an incremental fix as there are still a few bugs/mem leaks with the switchout code. Particularly when switching from an O3CPU to a TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA I haven't encountered any more assertion failures; now the kernel will typically panic inside of simulation.
Diffstat (limited to 'src/mem/packet_queue.cc')
-rw-r--r--src/mem/packet_queue.cc6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mem/packet_queue.cc b/src/mem/packet_queue.cc
index ab50fd567..77fba8883 100644
--- a/src/mem/packet_queue.cc
+++ b/src/mem/packet_queue.cc
@@ -41,6 +41,7 @@
* Andreas Hansson
*/
+#include "debug/Drain.hh"
#include "debug/PacketQueue.hh"
#include "mem/packet_queue.hh"
@@ -168,7 +169,9 @@ PacketQueue::scheduleSend(Tick time)
em.schedule(&sendEvent, std::max(nextReady, curTick() + 1));
} else {
// no more to send, so if we're draining, we may be done
- if (drainEvent && !sendEvent.scheduled()) {
+ if (drainEvent && transmitList.empty() && !sendEvent.scheduled()) {
+ DPRINTF(Drain, "PacketQueue done draining,"
+ "processing drain event\n");
drainEvent->process();
drainEvent = NULL;
}
@@ -201,6 +204,7 @@ PacketQueue::drain(Event *de)
{
if (transmitList.empty() && !sendEvent.scheduled())
return 0;
+ DPRINTF(Drain, "PacketQueue not drained\n");
drainEvent = de;
return 1;
}