util: do checkpoint aggregation more cleanly, fix last changeset.

1) Move alpha-specific code out of page_table.cc:serialize().
2) Begin serializing M5_pid and unserializing it, but adding an function to do optional paramIn so that old checkpoints don't need to be fixed up.
3) Fix up alpha startup code so that the unserialized M5_pid value is properly written to DTB_IPR_ASN.
4) Fix the memory unserialize that I forgot somehow in the last changeset.
5) Add in an agg_se.py to handle aggregated checkpoints. --bench foo-bar plus positional arguments foo bar are the only changes in usage from se.py.
Note this aggregation stuff has only been tested for Alpha and nothing else, though it should take a very minimal amount of work to get it to work with another ISA.

1 files changed, 0 insertions, 10 deletions

diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index 88cfdfeb7..bcaf5582a 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -223,15 +223,5 @@ PageTable::unserialize(Checkpoint *cp, const std::string &section)
         pTable[vaddr] = *entry;
         ++i;
     }
-
-    process->M5_pid = pTable[vaddr].asn;
-
-#if THE_ISA == ALPHA_ISA
-    // The IPR_DTB_ASN misc reg must be set in Alpha for the tlb to work 
-    // correctly
-    int id = process->contextIds[0];
-    ThreadContext *tc = process->system->getThreadContext(id);
-    tc->setMiscRegNoEffect(IPR_DTB_ASN, process->M5_pid << 57);
-#endif
 }