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authorLisa Hsu <Lisa.Hsu@amd.com>2010-01-18 14:33:02 -0800
committerLisa Hsu <Lisa.Hsu@amd.com>2010-01-18 14:33:02 -0800
commit0484432a7ca177d52fa98746b16c92805df73189 (patch)
tree2ef87808c118539c446b3c5f09e342bf1b434af8 /src/mem/page_table.cc
parentde904a6d396f01a42da5399b2798568c61abeeea (diff)
parent4a40ac71f8679ea7c15efb45afd522bf4d3b3e73 (diff)
downloadgem5-0484432a7ca177d52fa98746b16c92805df73189.tar.xz
Automated merge with ssh://hsul@localhost:4444//repo/m5
Diffstat (limited to 'src/mem/page_table.cc')
-rw-r--r--src/mem/page_table.cc12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index 4bc3a4434..88cfdfeb7 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -222,6 +222,16 @@ PageTable::unserialize(Checkpoint *cp, const std::string &section)
entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
pTable[vaddr] = *entry;
++i;
- }
+ }
+
+ process->M5_pid = pTable[vaddr].asn;
+
+#if THE_ISA == ALPHA_ISA
+ // The IPR_DTB_ASN misc reg must be set in Alpha for the tlb to work
+ // correctly
+ int id = process->contextIds[0];
+ ThreadContext *tc = process->system->getThreadContext(id);
+ tc->setMiscRegNoEffect(IPR_DTB_ASN, process->M5_pid << 57);
+#endif
}