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authorGabe Black <gabeblack@google.com>2018-01-08 23:37:57 -0800
committerGabe Black <gabeblack@google.com>2018-01-23 20:39:17 +0000
commita4e722725c90677d555675eca616c9d0990393f1 (patch)
treeed9a8268f73742fd4b4acbaf8e8434b67dc5fed7 /src/mem/page_table.hh
parentdb8c55dede65e07cb9ea8e95c48badd2ea24462f (diff)
downloadgem5-a4e722725c90677d555675eca616c9d0990393f1.tar.xz
tarch, mem: Abstract the data stored in the SE page tables.
Rather than store the actual TLB entry that corresponds to a mapping, we can just store some abstracted information (address, a few flags) and then let the caller turn that into the appropriate entry. There could potentially be some small amount of overhead from creating entries vs. storing them and just installing them, but it's likely pretty minimal since that only happens on a TLB miss (ideally rare), and, if it is problematic, there could be some preallocated TLB entries which are just minimally filled in as necessary. This has the nice effect of finally making the page tables ISA agnostic. Change-Id: I11e630f60682f0a0029b0683eb8ff0135fbd4317 Reviewed-on: https://gem5-review.googlesource.com/7350 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/mem/page_table.hh')
-rw-r--r--src/mem/page_table.hh25
1 files changed, 17 insertions, 8 deletions
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 733cdd2e3..fc0c0923e 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -40,11 +40,8 @@
#include <string>
#include <unordered_map>
-#include "arch/isa_traits.hh"
-#include "arch/tlb.hh"
#include "base/intmath.hh"
#include "base/types.hh"
-#include "config/the_isa.hh"
#include "mem/request.hh"
#include "sim/serialize.hh"
@@ -52,15 +49,25 @@ class ThreadContext;
class EmulationPageTable : public Serializable
{
+ public:
+ struct Entry
+ {
+ Addr paddr;
+ uint64_t flags;
+
+ Entry(Addr paddr, uint64_t flags) : paddr(paddr), flags(flags) {}
+ Entry() {}
+ };
+
protected:
- typedef std::unordered_map<Addr, TheISA::TlbEntry *> PTable;
+ typedef std::unordered_map<Addr, Entry> PTable;
typedef PTable::iterator PTableItr;
PTable pTable;
const Addr pageSize;
const Addr offsetMask;
- const uint64_t pid;
+ const uint64_t _pid;
const std::string _name;
public:
@@ -68,12 +75,14 @@ class EmulationPageTable : public Serializable
EmulationPageTable(
const std::string &__name, uint64_t _pid, Addr _pageSize) :
pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
- pid(_pid), _name(__name)
+ _pid(_pid), _name(__name)
{
assert(isPowerOf2(pageSize));
}
- virtual ~EmulationPageTable();
+ uint64_t pid() const { return _pid; };
+
+ virtual ~EmulationPageTable() {};
/* generic page table mapping flags
* unset | set
@@ -120,7 +129,7 @@ class EmulationPageTable : public Serializable
* @param vaddr The virtual address.
* @return The page table entry corresponding to vaddr.
*/
- virtual TheISA::TlbEntry *lookup(Addr vaddr);
+ const Entry *lookup(Addr vaddr);
/**
* Translate function