Significant rework of Packet class interface:

- new constructor guarantees initialization of most fields
- flags track status of non-guaranteed fields (addr, size, src)
- accessor functions (getAddr() etc.) check status on access
- Command & Result classes are nested in Packet class scope
- Command now built from vector of behavior bits
- string version of Command for tracing
- reinitFromRequest() and makeTimingResponse() encapsulate
common manipulations of existing packets

src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/timing.cc:
src/dev/alpha_console.cc:
src/dev/ide_ctrl.cc:
src/dev/io_device.cc:
src/dev/io_device.hh:
src/dev/isa_fake.cc:
src/dev/ns_gige.cc:
src/dev/pciconfigall.cc:
src/dev/sinic.cc:
src/dev/tsunami_cchip.cc:
src/dev/tsunami_io.cc:
src/dev/tsunami_pchip.cc:
src/dev/uart8250.cc:
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/physical.cc:
src/mem/port.cc:
src/mem/port.hh:
src/mem/request.hh:
    Update for new Packet interface.

--HG--
extra : convert_revision : 9973d09ea4fa61795f23772a7d3995fa4df5c269

1 files changed, 11 insertions, 9 deletions

diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index ae27d762f..26dbef0cd 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -128,7 +128,7 @@ PhysicalMemory::doTimingAccess (Packet *pkt, MemoryPort* memoryPort)
     doFunctionalAccess(pkt);
 
     // turn packet around to go back to requester
-    pkt->dest = pkt->src;
+    pkt->makeTimingResponse();
     MemResponseEvent* response = new MemResponseEvent(pkt, memoryPort);
     response->schedule(curTick + lat);
 
@@ -146,16 +146,18 @@ PhysicalMemory::doAtomicAccess(Packet *pkt)
 void
 PhysicalMemory::doFunctionalAccess(Packet *pkt)
 {
-    assert(pkt->addr + pkt->size < pmem_size);
+    assert(pkt->getAddr() + pkt->getSize() < pmem_size);
 
     switch (pkt->cmd) {
-      case Read:
-        memcpy(pkt->getPtr<uint8_t>(), pmem_addr + pkt->addr - base_addr,
-                pkt->size);
+      case Packet::ReadReq:
+        memcpy(pkt->getPtr<uint8_t>(),
+               pmem_addr + pkt->getAddr() - base_addr,
+               pkt->getSize());
         break;
-      case Write:
-        memcpy(pmem_addr + pkt->addr - base_addr, pkt->getPtr<uint8_t>(),
-                pkt->size);
+      case Packet::WriteReq:
+        memcpy(pmem_addr + pkt->getAddr() - base_addr,
+               pkt->getPtr<uint8_t>(),
+               pkt->getSize());
         // temporary hack: will need to add real LL/SC implementation
         // for cacheless systems later.
         if (pkt->req->getFlags() & LOCKED) {
@@ -166,7 +168,7 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt)
         panic("unimplemented");
     }
 
-    pkt->result = Success;
+    pkt->result = Packet::Success;
 }
 
 Port *