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authorSteve Reinhardt <stever@eecs.umich.edu>2007-05-19 00:24:34 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2007-05-19 00:24:34 -0400
commit0305159abf40765c6b8c506c777e3f62f3b6227e (patch)
tree9e6f19f64d626708141076ebbb4daa44fbe513ba /src/mem/physical.hh
parenta8278c3bde2ba9abc2820afafa9d0e766e36b2c8 (diff)
downloadgem5-0305159abf40765c6b8c506c777e3f62f3b6227e.tar.xz
PhysicalMemory has vector of uniform ports instead of one special one.
configs/example/memtest.py: PhysicalMemory has vector of uniform ports instead of one special one. Other updates to fix obsolete brokenness. src/mem/physical.cc: src/mem/physical.hh: src/python/m5/objects/PhysicalMemory.py: Have vector of uniform ports instead of one special one. src/python/swig/pyobject.cc: Add comment. --HG-- extra : convert_revision : a4a764dcdcd9720bcd07c979d0ece311fc8cb4f1
Diffstat (limited to 'src/mem/physical.hh')
-rw-r--r--src/mem/physical.hh3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index f7200b502..e3355d6aa 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -141,9 +141,10 @@ class PhysicalMemory : public MemObject
}
uint8_t *pmemAddr;
- MemoryPort *port;
int pagePtr;
Tick lat;
+ std::vector<MemoryPort*> ports;
+ typedef std::vector<MemoryPort*>::iterator PortIterator;
public:
Addr new_page();