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author | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-17 17:27:53 -0700 |
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committer | Steve Reinhardt <stever@eecs.umich.edu> | 2007-06-17 17:27:53 -0700 |
commit | 35cf19d441ed15d054d00674ec67ab5bc769f6d7 (patch) | |
tree | 86a97bf419e3c46834a446039ef8f4a85f74b7cc /src/mem/physical.hh | |
parent | a9b7c558fd6c00dacbdf36f4617c03a19c198b08 (diff) | |
download | gem5-35cf19d441ed15d054d00674ec67ab5bc769f6d7.tar.xz |
More major reorg of cache. Seems to work for atomic mode now,
timing mode still broken.
configs/example/memtest.py:
Revamp options.
src/cpu/memtest/memtest.cc:
No need for memory initialization.
No need to make atomic response... memory system should do that now.
src/cpu/memtest/memtest.hh:
MemTest really doesn't want to snoop.
src/mem/bridge.cc:
checkFunctional() cleanup.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/miss/SConscript:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/tport.cc:
More major reorg. Seems to work for atomic mode now,
timing mode still broken.
--HG--
extra : convert_revision : 7e70dfc4a752393b911880ff028271433855ae87
Diffstat (limited to 'src/mem/physical.hh')
-rw-r--r-- | src/mem/physical.hh | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/src/mem/physical.hh b/src/mem/physical.hh index b9af5d334..8b13d32c1 100644 --- a/src/mem/physical.hh +++ b/src/mem/physical.hh @@ -112,12 +112,12 @@ class PhysicalMemory : public MemObject // inline a quick check for an empty locked addr list (hopefully // the common case), and do the full list search (if necessary) in // this out-of-line function - bool checkLockedAddrList(Request *req); + bool checkLockedAddrList(PacketPtr pkt); // Record the address of a load-locked operation so that we can // clear the execution context's lock flag if a matching store is // performed - void trackLoadLocked(Request *req); + void trackLoadLocked(PacketPtr pkt); // Compare a store address with any locked addresses so we can // clear the lock flag appropriately. Return value set to 'false' @@ -126,17 +126,18 @@ class PhysicalMemory : public MemObject // requesting execution context), 'true' otherwise. Note that // this method must be called on *all* stores since even // non-conditional stores must clear any matching lock addresses. - bool writeOK(Request *req) { + bool writeOK(PacketPtr pkt) { + Request *req = pkt->req; if (lockedAddrList.empty()) { // no locked addrs: nothing to check, store_conditional fails - bool isLocked = req->isLocked(); + bool isLocked = pkt->isLocked(); if (isLocked) { req->setExtraData(0); } return !isLocked; // only do write if not an sc } else { // iterate over list... - return checkLockedAddrList(req); + return checkLockedAddrList(pkt); } } @@ -175,6 +176,7 @@ class PhysicalMemory : public MemObject unsigned int drain(Event *de); protected: + Tick doAtomicAccess(PacketPtr pkt); void doFunctionalAccess(PacketPtr pkt); virtual Tick calculateLatency(PacketPtr pkt); void recvStatusChange(Port::Status status); |