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authorAnthony Gutierrez <atgutier@umich.edu>2012-08-15 10:38:08 -0400
committerAnthony Gutierrez <atgutier@umich.edu>2012-08-15 10:38:08 -0400
commit0b3897fc90901953e9d016466c37ab507f85023c (patch)
tree0e8b1fec8d7c4871686903d573e9fd0fd8734d1e /src/mem/port.cc
parent5a648f2074caad8aee97e03f27e8eecc527a2cba (diff)
downloadgem5-0b3897fc90901953e9d016466c37ab507f85023c.tar.xz
O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
This patch fixes some problems with the drain/switchout functionality for the O3 cpu and for the ARM ISA and adds some useful debug print statements. This is an incremental fix as there are still a few bugs/mem leaks with the switchout code. Particularly when switching from an O3CPU to a TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA I haven't encountered any more assertion failures; now the kernel will typically panic inside of simulation.
Diffstat (limited to 'src/mem/port.cc')
-rw-r--r--src/mem/port.cc12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mem/port.cc b/src/mem/port.cc
index 36ca6304a..3827994fb 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -82,6 +82,12 @@ MasterPort::getSlavePort() const
}
void
+MasterPort::unBind()
+{
+ _slavePort = NULL;
+}
+
+void
MasterPort::bind(SlavePort& slave_port)
{
// master port keeps track of the slave port
@@ -167,6 +173,12 @@ SlavePort::~SlavePort()
}
void
+SlavePort::unBind()
+{
+ _masterPort = NULL;
+}
+
+void
SlavePort::bind(MasterPort& master_port)
{
_masterPort = &master_port;