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authorGabe Black <gabeblack@google.com>2019-03-07 00:45:09 -0800
committerGabe Black <gabeblack@google.com>2019-03-15 18:38:35 +0000
commit993c26938cb73239838893e3f5e46635392ea488 (patch)
tree9fdc5b947df798923263c7c8d30327cd5ef73383 /src/mem/port.cc
parent6e8be00dff5717ba6bd066749d1847ea48680878 (diff)
downloadgem5-993c26938cb73239838893e3f5e46635392ea488.tar.xz
mem: Move the Port base class into sim.
The Port class is going to be officially used for more than just memory system connections. Change-Id: I493e721f99051865c5f0c06946a2303ff723c2af Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17036 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/mem/port.cc')
-rw-r--r--src/mem/port.cc9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/mem/port.cc b/src/mem/port.cc
index ab62ccf1d..6f72bbd38 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -51,15 +51,6 @@
#include "base/trace.hh"
#include "mem/mem_object.hh"
-Port::Port(const std::string &_name, PortID _id)
- : portName(_name), id(_id)
-{
-}
-
-Port::~Port()
-{
-}
-
BaseMasterPort::BaseMasterPort(const std::string &name, PortID _id)
: Port(name, _id), _baseSlavePort(NULL)
{