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authorAndreas Hansson <andreas.hansson@arm.com>2012-01-17 12:55:08 -0600
committerAndreas Hansson <andreas.hansson@arm.com>2012-01-17 12:55:08 -0600
commitf85286b3debf4a4a94d3b959e5bb880be81bd692 (patch)
tree56a6be55a52d6cc6bb7e5d92fdcb25c79ad7d196 /src/mem/port.hh
parent06c39a154c4dc8fedcf9fbf77bbcf26f176c469c (diff)
downloadgem5-f85286b3debf4a4a94d3b959e5bb880be81bd692.tar.xz
MEM: Add port proxies instead of non-structural ports
Port proxies are used to replace non-structural ports, and thus enable all ports in the system to correspond to a structural entity. This has the advantage of accessing memory through the normal memory subsystem and thus allowing any constellation of distributed memories, address maps, etc. Most accesses are done through the "system port" that is used for loading binaries, debugging etc. For the entities that belong to the CPU, e.g. threads and thread contexts, they wrap the CPU data port in a port proxy. The following replacements are made: FunctionalPort > PortProxy TranslatingPort > SETranslatingPortProxy VirtualPort > FSTranslatingPortProxy --HG-- rename : src/mem/vport.cc => src/mem/fs_translating_port_proxy.cc rename : src/mem/vport.hh => src/mem/fs_translating_port_proxy.hh rename : src/mem/translating_port.cc => src/mem/se_translating_port_proxy.cc rename : src/mem/translating_port.hh => src/mem/se_translating_port_proxy.hh
Diffstat (limited to 'src/mem/port.hh')
-rw-r--r--src/mem/port.hh44
1 files changed, 0 insertions, 44 deletions
diff --git a/src/mem/port.hh b/src/mem/port.hh
index bb74bf497..c787f9f51 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -255,48 +255,4 @@ class Port : public EventManager
void blobHelper(Addr addr, uint8_t *p, int size, MemCmd cmd);
};
-/** A simple functional port that is only meant for one way communication to
- * physical memory. It is only meant to be used to load data into memory before
- * the simulation begins.
- */
-
-class FunctionalPort : public Port
-{
- public:
- FunctionalPort(const std::string &_name, MemObject *_owner = NULL)
- : Port(_name, _owner)
- {}
-
- protected:
- virtual bool recvTiming(PacketPtr pkt) { panic("FuncPort is UniDir");
- M5_DUMMY_RETURN }
- virtual Tick recvAtomic(PacketPtr pkt) { panic("FuncPort is UniDir");
- M5_DUMMY_RETURN }
- virtual void recvFunctional(PacketPtr pkt) { panic("FuncPort is UniDir"); }
- virtual void recvStatusChange(Status status) {}
-
- public:
- /** a write function that also does an endian conversion. */
- template <typename T>
- inline void writeHtoG(Addr addr, T d);
-
- /** a read function that also does an endian conversion. */
- template <typename T>
- inline T readGtoH(Addr addr);
-
- template <typename T>
- inline void write(Addr addr, T d)
- {
- writeBlob(addr, (uint8_t*)&d, sizeof(T));
- }
-
- template <typename T>
- inline T read(Addr addr)
- {
- T d;
- readBlob(addr, (uint8_t*)&d, sizeof(T));
- return d;
- }
-};
-
#endif //__MEM_PORT_HH__