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authorGabe Black <gblack@eecs.umich.edu>2011-02-01 18:28:41 -0800
committerGabe Black <gblack@eecs.umich.edu>2011-02-01 18:28:41 -0800
commit119f5f8e94e673b1495dccce03b54773dc18afea (patch)
treeff11fb58d39d12bd7c4fa5d94f629d718fe4e2ec /src/mem/port.hh
parent4b4cd0303ea0e3b23e641933dbf0da57d1483764 (diff)
downloadgem5-119f5f8e94e673b1495dccce03b54773dc18afea.tar.xz
X86: Add L1 caches for the TLB walkers.
Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly.
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