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author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2019-06-25 13:55:42 +0100 |
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committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2019-10-29 09:41:41 +0000 |
commit | e0de180ee4eb3316d2dd0d20320f2a1b310101bc (patch) | |
tree | 756c095d7d55f2eadb97f34bd1932f6c53ee0378 /src/mem/port_proxy.hh | |
parent | af48fb9373a16deecb04476fdcc7e5b7ffa3a63a (diff) | |
download | gem5-e0de180ee4eb3316d2dd0d20320f2a1b310101bc.tar.xz |
mem-cache: Fix MSHR whole line write tracking
The MSHR keeps track of outstanding writes and services them as a
whole line write whenever possible. To do this the outstanding writes
have to be compatible (e.g., not strictly ordered). Prior to this
change, due to this tracking mechanism, the MSHR would not service a
WriteLineReq with flags that do not allow merging as a full line write
even if it was the first target triggering an assertion. This
changeset fixes this bug.
Change-Id: I2cbf5ece0c108c1fcfe6855e8f194408d5ab8ce2
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22126
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/mem/port_proxy.hh')
0 files changed, 0 insertions, 0 deletions