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author | Andreas Hansson <andreas.hansson@arm.com> | 2013-09-04 13:22:57 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-09-04 13:22:57 -0400 |
commit | 19a5b68db7d73542833d94ec8b23cad6daf0a787 (patch) | |
tree | 589541b322580a54e539e24932d3b4bba05801db /src/mem/port_proxy.hh | |
parent | ea402970185d5df01dbad2c0f41b8d76d2eb01cd (diff) | |
download | gem5-19a5b68db7d73542833d94ec8b23cad6daf0a787.tar.xz |
arch: Resurrect the NOISA build target and rename it NULL
This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.
The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.
--HG--
rename : build_opts/NOISA => build_opts/NULL
rename : src/arch/noisa/SConsopts => src/arch/null/SConsopts
rename : src/arch/noisa/cpu_dummy.hh => src/arch/null/cpu_dummy.hh
rename : src/cpu/intr_control.cc => src/cpu/intr_control_noisa.cc
Diffstat (limited to 'src/mem/port_proxy.hh')
-rw-r--r-- | src/mem/port_proxy.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh index f1e01c385..1213daafa 100644 --- a/src/mem/port_proxy.hh +++ b/src/mem/port_proxy.hh @@ -60,7 +60,7 @@ #define __MEM_PORT_PROXY_HH__ #include "config/the_isa.hh" -#if THE_ISA != NO_ISA +#if THE_ISA != NULL_ISA #include "arch/isa_traits.hh" #endif @@ -127,7 +127,7 @@ class PortProxy template <typename T> void write(Addr address, T data) const; -#if THE_ISA != NO_ISA +#if THE_ISA != NULL_ISA /** * Read sizeof(T) bytes from address and return as object T. * Performs Guest to Host endianness transform. @@ -161,7 +161,7 @@ PortProxy::write(Addr address, T data) const writeBlob(address, (uint8_t*)&data, sizeof(T)); } -#if THE_ISA != NO_ISA +#if THE_ISA != NULL_ISA template <typename T> T PortProxy::readGtoH(Addr address) const |