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author | Nilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E) <nilay@cs.wisc.edu> | 2013-05-21 11:31:31 -0500 |
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committer | Nilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E) <nilay@cs.wisc.edu> | 2013-05-21 11:31:31 -0500 |
commit | 59a7abff29aa5a687e1693f003c20d7e2000c40a (patch) | |
tree | e1cf2cf822cf5b1002a6b72d8d613f65e0e1df8d /src/mem/protocol/MESI_CMP_directory-L1cache.sm | |
parent | d3c33d91b68e917478dba48c03a674b21ebd2747 (diff) | |
download | gem5-59a7abff29aa5a687e1693f003c20d7e2000c40a.tar.xz |
ruby: add stats to .sm files, remove cache profiler
This patch changes the way cache statistics are collected in ruby.
As of now, there is separate entity called CacheProfiler which holds
statistical variables for caches. The CacheMemory class defines different
functions for accessing the CacheProfiler. These functions are then invoked
in the .sm files. I find this approach opaque and prone to error. Secondly,
we probably should not be paying the cost of a function call for recording
statistics.
Instead, this patch allows for accessing statistical variables in the
.sm files. The collection would become transparent. Secondly, it would happen
in place, so no function calls. The patch also removes the CacheProfiler class.
--HG--
rename : src/mem/slicc/ast/InfixOperatorExprAST.py => src/mem/slicc/ast/OperatorExprAST.py
Diffstat (limited to 'src/mem/protocol/MESI_CMP_directory-L1cache.sm')
-rw-r--r-- | src/mem/protocol/MESI_CMP_directory-L1cache.sm | 46 |
1 files changed, 22 insertions, 24 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm index f8d731ee1..12e3a618b 100644 --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm @@ -874,16 +874,20 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") wakeUpBuffers(address); } - action(uu_profileInstMiss, "\ui", desc="Profile the demand miss") { - peek(mandatoryQueue_in, RubyRequest) { - L1IcacheMemory.profileMiss(in_msg); - } + action(uu_profileInstMiss, "\uim", desc="Profile the demand miss") { + ++L1IcacheMemory.demand_misses; } - action(uu_profileDataMiss, "\ud", desc="Profile the demand miss") { - peek(mandatoryQueue_in, RubyRequest) { - L1DcacheMemory.profileMiss(in_msg); - } + action(uu_profileInstHit, "\uih", desc="Profile the demand hit") { + ++L1IcacheMemory.demand_hits; + } + + action(uu_profileDataMiss, "\udm", desc="Profile the demand miss") { + ++L1DcacheMemory.demand_misses; + } + + action(uu_profileDataHit, "\udh", desc="Profile the demand hit") { + ++L1DcacheMemory.demand_hits; } action(po_observeMiss, "\po", desc="Inform the prefetcher about the miss") { @@ -1024,8 +1028,15 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } // Transitions from Shared - transition(S, {Load,Ifetch}) { + transition({S,E,M}, Load) { + h_load_hit; + uu_profileDataHit; + k_popMandatoryQueue; + } + + transition({S,E,M}, Ifetch) { h_load_hit; + uu_profileInstHit; k_popMandatoryQueue; } @@ -1049,13 +1060,9 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") // Transitions from Exclusive - transition(E, {Load, Ifetch}) { - h_load_hit; - k_popMandatoryQueue; - } - - transition(E, Store, M) { + transition({E,M}, Store, M) { hh_store_hit; + uu_profileDataHit; k_popMandatoryQueue; } @@ -1087,15 +1094,6 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") } // Transitions from Modified - transition(M, {Load, Ifetch}) { - h_load_hit; - k_popMandatoryQueue; - } - - transition(M, Store) { - hh_store_hit; - k_popMandatoryQueue; - } transition(M, L1_Replacement, M_I) { forward_eviction_to_cpu; |