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author | Nilay Vaish <nilay@cs.wisc.edu> | 2011-06-08 11:58:09 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2011-06-08 11:58:09 -0500 |
commit | 67bb3070032fcb944a63aabb4ecfff692840e7bf (patch) | |
tree | 104a8558a460aed6bc716f624bdd156b8f12f28d /src/mem/protocol/MESI_CMP_directory-L2cache.sm | |
parent | 1f7a6274017821d58f3087120079477ac211ceaf (diff) | |
download | gem5-67bb3070032fcb944a63aabb4ecfff692840e7bf.tar.xz |
Ruby: Correctly set access permissions for directory entries
The access permissions for the directory entries are not being set correctly.
This is because pointers are not used for handling directory entries.
function. get and set functions for access permissions have been added to the
Controller state machine. The changePermission() function provided by the
AbstractEntry and AbstractCacheEntry classes has been exposed to SLICC
code once again. The set_permission() functionality has been removed.
NOTE: Each protocol will have to define these get and set functions in order
to compile successfully.
Diffstat (limited to 'src/mem/protocol/MESI_CMP_directory-L2cache.sm')
-rw-r--r-- | src/mem/protocol/MESI_CMP_directory-L2cache.sm | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm index 771a2dfb2..6044f5233 100644 --- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm @@ -202,7 +202,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") return L2Cache_State_to_string(getState(tbe, cache_entry, addr)); } - // when is this called void setState(TBE tbe, Entry cache_entry, Address addr, State state) { // MUST CHANGE @@ -215,6 +214,26 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } } + AccessPermission getAccessPermission(Address addr) { + TBE tbe := L2_TBEs[addr]; + if(is_valid(tbe)) { + return L2Cache_State_to_permission(tbe.TBEState); + } + + Entry cache_entry := getCacheEntry(addr); + if(is_valid(cache_entry)) { + return L2Cache_State_to_permission(cache_entry.CacheState); + } + + return AccessPermission:NotPresent; + } + + void setAccessPermission(Entry cache_entry, Address addr, State state) { + if (is_valid(cache_entry)) { + cache_entry.changePermission(L2Cache_State_to_permission(state)); + } + } + Event L1Cache_request_type_to_event(CoherenceRequestType type, Address addr, MachineID requestor, Entry cache_entry) { if(type == CoherenceRequestType:GETS) { |