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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-23 16:41:58 -0800 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-23 16:41:58 -0800 |
| commit | 3bc33eeaea3172fa65ec40f1e0eef9554eb51d8f (patch) | |
| tree | 714c65fbe63ab35f85b813842093fe42515d272a /src/mem/protocol/MESI_CMP_directory-L2cache.sm | |
| parent | c09a33e5d50bf445545b053d8f15a654ca9c302b (diff) | |
| download | gem5-3bc33eeaea3172fa65ec40f1e0eef9554eb51d8f.tar.xz | |
ruby: cleaned up access permission enum
Diffstat (limited to 'src/mem/protocol/MESI_CMP_directory-L2cache.sm')
| -rw-r--r-- | src/mem/protocol/MESI_CMP_directory-L2cache.sm | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm index c037527de..aeaf3d60d 100644 --- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm @@ -219,7 +219,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") } else if (state == State:M) { cache_entry.changePermission(AccessPermission:Read_Write); } else if (state == State:MT) { - cache_entry.changePermission(AccessPermission:Stale); + cache_entry.changePermission(AccessPermission:Invalid); } else { cache_entry.changePermission(AccessPermission:Busy); } |