diff options
author | Lena Olson <lena@cs.wisc.edu> | 2013-06-18 16:58:33 -0500 |
---|---|---|
committer | Lena Olson <lena@cs.wisc.edu> | 2013-06-18 16:58:33 -0500 |
commit | 7c39d5df7ea61a39ad1b9a3aa70d22f0e2943b21 (patch) | |
tree | d2d2ca457dd5a1d43ee2389ce7202b68f567b951 /src/mem/protocol/MESI_CMP_directory-dir.sm | |
parent | d06064c38613662dfbf68a701052278b4018de8c (diff) | |
download | gem5-7c39d5df7ea61a39ad1b9a3aa70d22f0e2943b21.tar.xz |
ruby: restrict Address to being a type and not a variable name
Change all occurrances of Address as a variable name to instead use Addr.
Address is an allowed name in slicc even when Address is also being used as a
type, leading to declarations of "Address Address". While this works, it
prevents adding another field of type Address because the compiler then thinks
Address is a variable name, not type.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/mem/protocol/MESI_CMP_directory-dir.sm')
-rw-r--r-- | src/mem/protocol/MESI_CMP_directory-dir.sm | 52 |
1 files changed, 26 insertions, 26 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-dir.sm b/src/mem/protocol/MESI_CMP_directory-dir.sm index 665e3461e..26a5c38df 100644 --- a/src/mem/protocol/MESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MESI_CMP_directory-dir.sm @@ -201,13 +201,13 @@ machine(Directory, "MESI_CMP_filter_directory protocol") peek(requestNetwork_in, RequestMsg) { assert(in_msg.Destination.isElement(machineID)); if (isGETRequest(in_msg.Type)) { - trigger(Event:Fetch, in_msg.Address, TBEs[in_msg.Address]); + trigger(Event:Fetch, in_msg.Addr, TBEs[in_msg.Addr]); } else if (in_msg.Type == CoherenceRequestType:DMA_READ) { - trigger(Event:DMA_READ, makeLineAddress(in_msg.Address), - TBEs[makeLineAddress(in_msg.Address)]); + trigger(Event:DMA_READ, makeLineAddress(in_msg.Addr), + TBEs[makeLineAddress(in_msg.Addr)]); } else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) { - trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address), - TBEs[makeLineAddress(in_msg.Address)]); + trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Addr), + TBEs[makeLineAddress(in_msg.Addr)]); } else { DPRINTF(RubySlicc, "%s\n", in_msg); error("Invalid message"); @@ -221,9 +221,9 @@ machine(Directory, "MESI_CMP_filter_directory protocol") peek(responseNetwork_in, ResponseMsg) { assert(in_msg.Destination.isElement(machineID)); if (in_msg.Type == CoherenceResponseType:MEMORY_DATA) { - trigger(Event:Data, in_msg.Address, TBEs[in_msg.Address]); + trigger(Event:Data, in_msg.Addr, TBEs[in_msg.Addr]); } else if (in_msg.Type == CoherenceResponseType:ACK) { - trigger(Event:CleanReplacement, in_msg.Address, TBEs[in_msg.Address]); + trigger(Event:CleanReplacement, in_msg.Addr, TBEs[in_msg.Addr]); } else { DPRINTF(RubySlicc, "%s\n", in_msg.Type); error("Invalid message"); @@ -237,9 +237,9 @@ machine(Directory, "MESI_CMP_filter_directory protocol") if (memQueue_in.isReady()) { peek(memQueue_in, MemoryMsg) { if (in_msg.Type == MemoryRequestType:MEMORY_READ) { - trigger(Event:Memory_Data, in_msg.Address, TBEs[in_msg.Address]); + trigger(Event:Memory_Data, in_msg.Addr, TBEs[in_msg.Addr]); } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) { - trigger(Event:Memory_Ack, in_msg.Address, TBEs[in_msg.Address]); + trigger(Event:Memory_Ack, in_msg.Addr, TBEs[in_msg.Addr]); } else { DPRINTF(RubySlicc, "%s\n", in_msg.Type); error("Invalid message"); @@ -253,7 +253,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") action(a_sendAck, "a", desc="Send ack to L2") { peek(responseNetwork_in, ResponseMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:MEMORY_ACK; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Sender); @@ -265,7 +265,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") action(d_sendData, "d", desc="Send data to requestor") { peek(memQueue_in, MemoryMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:MEMORY_DATA; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.OriginalRequestorMachId); @@ -280,7 +280,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") action(aa_sendAck, "aa", desc="Send ack to L2") { peek(memQueue_in, MemoryMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:MEMORY_ACK; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.OriginalRequestorMachId); @@ -308,13 +308,13 @@ machine(Directory, "MESI_CMP_filter_directory protocol") action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") { peek(requestNetwork_in, RequestMsg) { enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; out_msg.OriginalRequestorMachId := in_msg.Requestor; out_msg.MessageSize := in_msg.MessageSize; out_msg.Prefetch := in_msg.Prefetch; - out_msg.DataBlk := getDirectoryEntry(in_msg.Address).DataBlk; + out_msg.DataBlk := getDirectoryEntry(in_msg.Addr).DataBlk; DPRINTF(RubySlicc, "%s\n", out_msg); } @@ -324,7 +324,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") action(qw_queueMemoryWBRequest, "qw", desc="Queue off-chip writeback request") { peek(responseNetwork_in, ResponseMsg) { enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; out_msg.Sender := machineID; out_msg.OriginalRequestorMachId := in_msg.Sender; @@ -339,16 +339,16 @@ machine(Directory, "MESI_CMP_filter_directory protocol") action(m_writeDataToMemory, "m", desc="Write dirty writeback to memory") { peek(responseNetwork_in, ResponseMsg) { - getDirectoryEntry(in_msg.Address).DataBlk := in_msg.DataBlk; + getDirectoryEntry(in_msg.Addr).DataBlk := in_msg.DataBlk; DPRINTF(RubySlicc, "Address: %s, Data Block: %s\n", - in_msg.Address, in_msg.DataBlk); + in_msg.Addr, in_msg.DataBlk); } } //added by SS for dma action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") { peek(requestNetwork_in, RequestMsg) { enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_READ; out_msg.Sender := machineID; out_msg.OriginalRequestorMachId := machineID; @@ -366,7 +366,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") { peek(memQueue_in, MemoryMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be out_msg.Destination.add(map_Address_to_DMA(address)); @@ -377,14 +377,14 @@ machine(Directory, "MESI_CMP_filter_directory protocol") action(dw_writeDMAData, "dw", desc="DMA Write data to memory") { peek(requestNetwork_in, RequestMsg) { - getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len); + getDirectoryEntry(address).DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Addr), in_msg.Len); } } action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") { peek(requestNetwork_in, RequestMsg) { enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; out_msg.OriginalRequestorMachId := machineID; //out_msg.DataBlk := in_msg.DataBlk; @@ -401,7 +401,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") { enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Destination.add(map_Address_to_DMA(address)); out_msg.MessageSize := MessageSizeType:Writeback_Control; @@ -428,7 +428,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") { peek(requestNetwork_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:INV; out_msg.Sender := machineID; out_msg.Destination := getDirectoryEntry(address).Owner; @@ -441,7 +441,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") { peek(responseNetwork_in, ResponseMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be out_msg.Destination.add(map_Address_to_DMA(address)); @@ -459,7 +459,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") TBEs.allocate(address); set_tbe(TBEs[address]); tbe.DataBlk := in_msg.DataBlk; - tbe.PhysicalAddress := in_msg.Address; + tbe.PhysicalAddress := in_msg.Addr; tbe.Len := in_msg.Len; } } @@ -477,7 +477,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") peek(responseNetwork_in, ResponseMsg) { enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := MemoryRequestType:MEMORY_WB; out_msg.OriginalRequestorMachId := in_msg.Sender; //out_msg.DataBlk := in_msg.DataBlk; |