ruby: removed unsupported protocol files

1 files changed, 0 insertions, 894 deletions

diff --git a/src/mem/protocol/MESI_SCMP_bankdirectory-L1cache.sm b/src/mem/protocol/MESI_SCMP_bankdirectory-L1cache.sm
deleted file mode 100644
index 6e707a431..000000000
--- a/src/mem/protocol/MESI_SCMP_bankdirectory-L1cache.sm
+++ /dev/null
@@ -1,894 +0,0 @@
-
-/*
- * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * $Id: MSI_MOSI_CMP_directory-L1cache.sm 1.10 05/01/19 15:55:40-06:00 beckmann@s0-28.cs.wisc.edu $
- *
- */
-
-
-machine(L1Cache, "MSI Directory L1 Cache CMP") {
-
-  // NODE L1 CACHE
-  // From this node's L1 cache TO the network
-  // a local L1 -> this L2 bank, currently ordered with directory forwarded requests
-  MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false";
-  // a local L1 -> this L2 bank
-  MessageBuffer responseFromL1Cache, network="To", virtual_network="3", ordered="false";
-  MessageBuffer unblockFromL1Cache, network="To", virtual_network="4", ordered="false";
-
-
-  // To this node's L1 cache FROM the network
-  // a L2 bank -> this L1
-  MessageBuffer requestToL1Cache, network="From", virtual_network="1", ordered="false";
-  // a L2 bank -> this L1
-  MessageBuffer responseToL1Cache, network="From", virtual_network="3", ordered="false";
-
-  // STATES
-  enumeration(State, desc="Cache states", default="L1Cache_State_I") {
-    // Base states
-    NP, desc="Not present in either cache";
-    I, desc="a L1 cache entry Idle";
-    S, desc="a L1 cache entry Shared";
-    E, desc="a L1 cache entry Exclusive";
-    M, desc="a L1 cache entry Modified", format="!b";
-
-    // Transient States
-    IS, desc="L1 idle, issued GETS, have not seen response yet";
-    IM, desc="L1 idle, issued GETX, have not seen response yet";
-    SM, desc="L1 idle, issued GETX, have not seen response yet";
-    IS_I, desc="L1 idle, issued GETS, saw Inv before data because directory doesn't block on GETS hit";
-
-    M_I, desc="L1 replacing, waiting for ACK";
-    E_I, desc="L1 replacing, waiting for ACK";
-
-  }
-
-  // EVENTS
-  enumeration(Event, desc="Cache events") {
-    // L1 events
-    Load,            desc="Load request from the home processor";
-    Ifetch,          desc="I-fetch request from the home processor";
-    Store,           desc="Store request from the home processor";
-
-    Inv,           desc="Invalidate request from L2 bank";
-
-    // internal generated request
-    L1_Replacement,  desc="L1 Replacement", format="!r";
-
-    // other requests
-    Fwd_GETX,   desc="GETX from other processor";
-    Fwd_GETS,   desc="GETS from other processor";
-    Fwd_GET_INSTR,   desc="GET_INSTR from other processor";
-
-    Data,       desc="Data for processor";
-    Data_Exclusive,       desc="Data for processor";
-    DataS_fromL1,       desc="data for GETS request, need to unblock directory";
-    Data_all_Acks,       desc="Data for processor, all acks";
-
-    Ack,        desc="Ack for processor";
-    Ack_all,      desc="Last ack for processor";
-
-    WB_Ack,        desc="Ack for replacement";
-  }
-
-  // TYPES
-
-  // CacheEntry
-  structure(Entry, desc="...", interface="AbstractCacheEntry" ) {
-    State CacheState,        desc="cache state";
-    DataBlock DataBlk,       desc="data for the block";
-    bool Dirty, default="false",   desc="data is dirty";
-  }
-
-  // TBE fields
-  structure(TBE, desc="...") {
-    Address Address,              desc="Physical address for this TBE";
-    State TBEState,        desc="Transient state";
-    DataBlock DataBlk,                desc="Buffer for the data block";
-    bool Dirty, default="false",   desc="data is dirty";
-    bool isPrefetch,       desc="Set if this was caused by a prefetch";
-    int pendingAcks, default="0", desc="number of pending acks";
-  }
-
-  external_type(CacheMemory) {
-    bool cacheAvail(Address);
-    Address cacheProbe(Address);
-    void allocate(Address);
-    void deallocate(Address);
-    Entry lookup(Address);
-    void changePermission(Address, AccessPermission);
-    bool isTagPresent(Address);
-  }
-
-  external_type(TBETable) {
-    TBE lookup(Address);
-    void allocate(Address);
-    void deallocate(Address);
-    bool isPresent(Address);
-  }
-
-  TBETable L1_TBEs, template_hack="<L1Cache_TBE>";
-
-  CacheMemory L1IcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1I"', abstract_chip_ptr="true";
-  CacheMemory L1DcacheMemory, template_hack="<L1Cache_Entry>", constructor_hack='L1_CACHE_NUM_SETS_BITS,L1_CACHE_ASSOC,MachineType_L1Cache,int_to_string(i)+"_L1D"', abstract_chip_ptr="true";
-
-  MessageBuffer mandatoryQueue, ordered="false", rank="100", abstract_chip_ptr="true";
-
-  Sequencer sequencer, abstract_chip_ptr="true", constructor_hack="i";
-
-  int cache_state_to_int(State state);
-
-  // inclusive cache returns L1 entries only
-  Entry getL1CacheEntry(Address addr), return_by_ref="yes" {
-    if (L1DcacheMemory.isTagPresent(addr)) {
-      return L1DcacheMemory[addr];
-    } else {
-      return L1IcacheMemory[addr];
-    }
-  }
-
-  void changeL1Permission(Address addr, AccessPermission permission) {
-    if (L1DcacheMemory.isTagPresent(addr)) {
-      return L1DcacheMemory.changePermission(addr, permission);
-    } else if(L1IcacheMemory.isTagPresent(addr)) {
-      return L1IcacheMemory.changePermission(addr, permission);
-    } else {
-      error("cannot change permission, L1 block not present");
-    }
-  }
-
-  bool isL1CacheTagPresent(Address addr) {
-    return (L1DcacheMemory.isTagPresent(addr) || L1IcacheMemory.isTagPresent(addr));
-  }
-
-  State getState(Address addr) {
-    if((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == true){
-      DEBUG_EXPR(id);
-      DEBUG_EXPR(addr);
-    }
-    assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
-
-    if(L1_TBEs.isPresent(addr)) {
-      return L1_TBEs[addr].TBEState;
-    } else if (isL1CacheTagPresent(addr)) {
-      return getL1CacheEntry(addr).CacheState;
-    }
-    return State:NP;
-  }
-
-
-  void setState(Address addr, State state) {
-    assert((L1DcacheMemory.isTagPresent(addr) && L1IcacheMemory.isTagPresent(addr)) == false);
-
-    // MUST CHANGE
-    if(L1_TBEs.isPresent(addr)) {
-      L1_TBEs[addr].TBEState := state;
-    }
-
-    if (isL1CacheTagPresent(addr)) {
-      getL1CacheEntry(addr).CacheState := state;
-
-      // Set permission
-      if (state == State:I) {
-        changeL1Permission(addr, AccessPermission:Invalid);
-      } else if (state == State:S || state == State:E) {
-        changeL1Permission(addr, AccessPermission:Read_Only);
-      } else if (state == State:M) {
-        changeL1Permission(addr, AccessPermission:Read_Write);
-      } else {
-        changeL1Permission(addr, AccessPermission:Busy);
-      }
-    }
-  }
-
-  Event mandatory_request_type_to_event(CacheRequestType type) {
-    if (type == CacheRequestType:LD) {
-      return Event:Load;
-    } else if (type == CacheRequestType:IFETCH) {
-      return Event:Ifetch;
-    } else if ((type == CacheRequestType:ST) || (type == CacheRequestType:ATOMIC)) {
-      return Event:Store;
-    } else {
-      error("Invalid CacheRequestType");
-    }
-  }
-
-  GenericMachineType getNondirectHitMachType(Address addr, MachineID sender) {
-    if (machineIDToMachineType(sender) == MachineType:L1Cache) {
-      return GenericMachineType:L1Cache_wCC;  // NOTE direct L1 hits should not call this
-    } else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
-      return GenericMachineType:L2Cache;
-    } else {
-      return ConvertMachToGenericMach(machineIDToMachineType(sender));
-    }
-  }
-
-
-
-  out_port(requestIntraChipL1Network_out, RequestMsg, requestFromL1Cache);
-  out_port(responseIntraChipL1Network_out, ResponseMsg, responseFromL1Cache);
-  out_port(unblockNetwork_out, ResponseMsg, unblockFromL1Cache);
-
-  // Response IntraChip L1 Network - response msg to this L1 cache
-  in_port(responseIntraChipL1Network_in, ResponseMsg, responseToL1Cache) {
-    if (responseIntraChipL1Network_in.isReady()) {
-      peek(responseIntraChipL1Network_in, ResponseMsg) {
-        assert(in_msg.Destination.isElement(machineID));
-        if(in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) {
-          trigger(Event:Data_Exclusive, in_msg.Address);
-        } else if(in_msg.Type == CoherenceResponseType:DATA) {
-          if ( (getState(in_msg.Address) == State:IS || getState(in_msg.Address) == State:IS_I) &&
-                machineIDToMachineType(in_msg.Sender) == MachineType:L1Cache ) {
-
-              trigger(Event:DataS_fromL1, in_msg.Address);
-
-          } else if ( (L1_TBEs[in_msg.Address].pendingAcks - in_msg.AckCount) == 0 ) {
-            trigger(Event:Data_all_Acks, in_msg.Address);
-          } else {
-            trigger(Event:Data, in_msg.Address);
-          }
-        } else if (in_msg.Type == CoherenceResponseType:ACK) {
-          if ( (L1_TBEs[in_msg.Address].pendingAcks - in_msg.AckCount) == 0 ) {
-            trigger(Event:Ack_all, in_msg.Address);
-          } else {
-            trigger(Event:Ack, in_msg.Address);
-          }
-        } else if (in_msg.Type == CoherenceResponseType:WB_ACK) {
-          trigger(Event:WB_Ack, in_msg.Address);
-        } else {
-          error("Invalid L1 response type");
-        }
-      }
-    }
-  }
-
-  // Request InterChip network - request from this L1 cache to the shared L2
-  in_port(requestIntraChipL1Network_in, RequestMsg, requestToL1Cache) {
-    if(requestIntraChipL1Network_in.isReady()) {
-      peek(requestIntraChipL1Network_in, RequestMsg) {
-        assert(in_msg.Destination.isElement(machineID));
-        if (in_msg.Type == CoherenceRequestType:INV) {
-          trigger(Event:Inv, in_msg.Address);
-        } else if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:UPGRADE) {
-          // upgrade transforms to GETX due to race
-          trigger(Event:Fwd_GETX, in_msg.Address);
-        } else if (in_msg.Type == CoherenceRequestType:GETS) {
-          trigger(Event:Fwd_GETS, in_msg.Address);
-        } else if (in_msg.Type == CoherenceRequestType:GET_INSTR) {
-          trigger(Event:Fwd_GET_INSTR, in_msg.Address);
-        } else {
-          error("Invalid forwarded request type");
-        }
-      }
-    }
-  }
-
-  // Mandatory Queue betweens Node's CPU and it's L1 caches
-  in_port(mandatoryQueue_in, CacheMsg, mandatoryQueue, desc="...") {
-    if (mandatoryQueue_in.isReady()) {
-      peek(mandatoryQueue_in, CacheMsg) {
-
-        // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache
-
-        if (in_msg.Type == CacheRequestType:IFETCH) {
-          // ** INSTRUCTION ACCESS ***
-
-          // Check to see if it is in the OTHER L1
-          if (L1DcacheMemory.isTagPresent(in_msg.Address)) {
-            // The block is in the wrong L1, put the request on the queue to the shared L2
-            trigger(Event:L1_Replacement, in_msg.Address);
-          }
-          if (L1IcacheMemory.isTagPresent(in_msg.Address)) {
-            // The tag matches for the L1, so the L1 asks the L2 for it.
-            trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
-          } else {
-            if (L1IcacheMemory.cacheAvail(in_msg.Address)) {
-              // L1 does't have the line, but we have space for it in the L1 so let's see if the L2 has it
-              trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
-            } else {
-              // No room in the L1, so we need to make room in the L1
-              trigger(Event:L1_Replacement, L1IcacheMemory.cacheProbe(in_msg.Address));
-            }
-          }
-        } else {
-          // *** DATA ACCESS ***
-
-          // Check to see if it is in the OTHER L1
-          if (L1IcacheMemory.isTagPresent(in_msg.Address)) {
-            // The block is in the wrong L1, put the request on the queue to the shared L2
-            trigger(Event:L1_Replacement, in_msg.Address);
-          }
-          if (L1DcacheMemory.isTagPresent(in_msg.Address)) {
-            // The tag matches for the L1, so the L1 ask the L2 for it
-            trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
-          } else {
-            if (L1DcacheMemory.cacheAvail(in_msg.Address)) {
-              // L1 does't have the line, but we have space for it in the L1 let's see if the L2 has it
-              trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.Address);
-            } else {
-              // No room in the L1, so we need to make room in the L1
-              trigger(Event:L1_Replacement, L1DcacheMemory.cacheProbe(in_msg.Address));
-            }
-          }
-        }
-      }
-    }
-  }
-
-  // ACTIONS
-  action(a_issueGETS, "a", desc="Issue GETS") {
-    peek(mandatoryQueue_in, CacheMsg) {
-      enqueue(requestIntraChipL1Network_out, RequestMsg, latency="L1_REQUEST_LATENCY") {
-        out_msg.Address := address;
-        out_msg.Type := CoherenceRequestType:GETS;
-        out_msg.Requestor := machineID;
-        out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
-        DEBUG_EXPR(address);
-        DEBUG_EXPR(out_msg.Destination);
-        out_msg.MessageSize := MessageSizeType:Control;
-        out_msg.Prefetch := in_msg.Prefetch;
-        out_msg.AccessMode := in_msg.AccessMode;
-      }
-    }
-  }
-
-  action(ai_issueGETINSTR, "ai", desc="Issue GETINSTR") {
-    peek(mandatoryQueue_in, CacheMsg) {
-      enqueue(requestIntraChipL1Network_out, RequestMsg, latency="L1_REQUEST_LATENCY") {
-        out_msg.Address := address;
-        out_msg.Type := CoherenceRequestType:GET_INSTR;
-        out_msg.Requestor := machineID;
-        out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
-        DEBUG_EXPR(address);
-        DEBUG_EXPR(out_msg.Destination);
-        out_msg.MessageSize := MessageSizeType:Control;
-        out_msg.Prefetch := in_msg.Prefetch;
-        out_msg.AccessMode := in_msg.AccessMode;
-      }
-    }
-  }
-
-
-  action(b_issueGETX, "b", desc="Issue GETX") {
-    peek(mandatoryQueue_in, CacheMsg) {
-      enqueue(requestIntraChipL1Network_out, RequestMsg, latency="L1_REQUEST_LATENCY") {
-        out_msg.Address := address;
-        out_msg.Type := CoherenceRequestType:GETX;
-        out_msg.Requestor := machineID;
-        DEBUG_EXPR(machineID);
-        out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
-        DEBUG_EXPR(address);
-        DEBUG_EXPR(out_msg.Destination);
-        out_msg.MessageSize := MessageSizeType:Control;
-        out_msg.Prefetch := in_msg.Prefetch;
-        out_msg.AccessMode := in_msg.AccessMode;
-      }
-    }
-  }
-
-  action(c_issueUPGRADE, "c", desc="Issue GETX") {
-    peek(mandatoryQueue_in, CacheMsg) {
-      enqueue(requestIntraChipL1Network_out, RequestMsg, latency="L1_REQUEST_LATENCY") {
-        out_msg.Address := address;
-        out_msg.Type := CoherenceRequestType:UPGRADE;
-        out_msg.Requestor := machineID;
-        out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
-        DEBUG_EXPR(address);
-        DEBUG_EXPR(out_msg.Destination);
-        out_msg.MessageSize := MessageSizeType:Control;
-        out_msg.Prefetch := in_msg.Prefetch;
-        out_msg.AccessMode := in_msg.AccessMode;
-      }
-    }
-  }
-
-  action(d_sendDataToRequestor, "d", desc="send data to requestor") {
-    peek(requestIntraChipL1Network_in, RequestMsg) {
-      enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
-        out_msg.Address := address;
-        out_msg.Type := CoherenceResponseType:DATA;
-        out_msg.DataBlk := getL1CacheEntry(address).DataBlk;
-        out_msg.Dirty := getL1CacheEntry(address).Dirty;
-        out_msg.Sender := machineID;
-        out_msg.Destination.add(in_msg.Requestor);
-        out_msg.MessageSize := MessageSizeType:Response_Data;
-      }
-    }
-  }
-
-  action(d2_sendDataToL2, "d2", desc="send data to the L2 cache because of M downgrade") {
-    enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
-      out_msg.Address := address;
-      out_msg.Type := CoherenceResponseType:DATA;
-      out_msg.DataBlk := getL1CacheEntry(address).DataBlk;
-      out_msg.Dirty := getL1CacheEntry(address).Dirty;
-      out_msg.Sender := machineID;
-      out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
-      out_msg.MessageSize := MessageSizeType:Response_Data;
-    }
-  }
-
-  action(dt_sendDataToRequestor_fromTBE, "dt", desc="send data to requestor") {
-    peek(requestIntraChipL1Network_in, RequestMsg) {
-      enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
-        out_msg.Address := address;
-        out_msg.Type := CoherenceResponseType:DATA;
-        out_msg.DataBlk := L1_TBEs[address].DataBlk;
-        out_msg.Dirty := L1_TBEs[address].Dirty;
-        out_msg.Sender := machineID;
-        out_msg.Destination.add(in_msg.Requestor);
-        out_msg.MessageSize := MessageSizeType:Response_Data;
-      }
-    }
-  }
-
-  action(d2t_sendDataToL2_fromTBE, "d2t", desc="send data to the L2 cache") {
-    enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
-      out_msg.Address := address;
-      out_msg.Type := CoherenceResponseType:DATA;
-      out_msg.DataBlk := L1_TBEs[address].DataBlk;
-      out_msg.Dirty := L1_TBEs[address].Dirty;
-      out_msg.Sender := machineID;
-      out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
-      out_msg.MessageSize := MessageSizeType:Response_Data;
-    }
-  }
-
-  action(e_sendAckToRequestor, "e", desc="send invalidate ack to requestor (could be L2 or L1)") {
-    peek(requestIntraChipL1Network_in, RequestMsg) {
-      enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
-        out_msg.Address := address;
-        out_msg.Type := CoherenceResponseType:ACK;
-        out_msg.Sender := machineID;
-        out_msg.Destination.add(in_msg.Requestor);
-        out_msg.MessageSize := MessageSizeType:Response_Control;
-      }
-    }
-  }
-
-  action(f_sendDataToL2, "f", desc="send data to the L2 cache") {
-    enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
-      out_msg.Address := address;
-      out_msg.Type := CoherenceResponseType:DATA;
-      out_msg.DataBlk := getL1CacheEntry(address).DataBlk;
-      out_msg.Dirty := getL1CacheEntry(address).Dirty;
-      out_msg.Sender := machineID;
-      out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
-      out_msg.MessageSize := MessageSizeType:Writeback_Data;
-    }
-  }
-
-  action(ft_sendDataToL2_fromTBE, "ft", desc="send data to the L2 cache") {
-    enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
-      out_msg.Address := address;
-      out_msg.Type := CoherenceResponseType:DATA;
-      out_msg.DataBlk := L1_TBEs[address].DataBlk;
-      out_msg.Dirty := L1_TBEs[address].Dirty;
-      out_msg.Sender := machineID;
-      out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
-      out_msg.MessageSize := MessageSizeType:Writeback_Data;
-    }
-  }
-
-  action(fi_sendInvAck, "fi", desc="send data to the L2 cache") {
-    peek(requestIntraChipL1Network_in, RequestMsg) {
-      enqueue(responseIntraChipL1Network_out, ResponseMsg, latency="L1_RESPONSE_LATENCY") {
-        out_msg.Address := address;
-        out_msg.Type := CoherenceResponseType:ACK;
-        out_msg.Sender := machineID;
-        out_msg.Destination.add(in_msg.Requestor);
-        out_msg.MessageSize := MessageSizeType:Response_Control;
-        out_msg.AckCount := 1;
-      }
-    }
-  }
-
-
-  action(g_issuePUTX, "g", desc="send data to the L2 cache") {
-    enqueue(requestIntraChipL1Network_out, RequestMsg, latency="L1_RESPONSE_LATENCY") {
-      out_msg.Address := address;
-      out_msg.Type := CoherenceRequestType:PUTX;
-      out_msg.DataBlk := getL1CacheEntry(address).DataBlk;
-      out_msg.Dirty := getL1CacheEntry(address).Dirty;
-      out_msg.Requestor:= machineID;
-      out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
-      if (getL1CacheEntry(address).Dirty) {
-        out_msg.MessageSize := MessageSizeType:Writeback_Data;
-      } else {
-        out_msg.MessageSize := MessageSizeType:Writeback_Control;
-      }
-    }
-  }
-
-  action(j_sendUnblock, "j", desc="send unblock to the L2 cache") {
-    enqueue(unblockNetwork_out, ResponseMsg, latency="1") {
-      out_msg.Address := address;
-      out_msg.Type := CoherenceResponseType:UNBLOCK;
-      out_msg.Sender := machineID;
-      out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
-      out_msg.MessageSize := MessageSizeType:Response_Control;
-    }
-  }
-
-  action(jj_sendExclusiveUnblock, "\j", desc="send unblock to the L2 cache") {
-    enqueue(unblockNetwork_out, ResponseMsg, latency="1") {
-      out_msg.Address := address;
-      out_msg.Type := CoherenceResponseType:EXCLUSIVE_UNBLOCK;
-      out_msg.Sender := machineID;
-      out_msg.Destination.add(map_L1CacheMachId_to_L2Cache(address, machineID));
-      out_msg.MessageSize := MessageSizeType:Response_Control;
-    }
-  }
-
-
-
-  action(h_load_hit, "h", desc="If not prefetch, notify sequencer the load completed.") {
-    DEBUG_EXPR(getL1CacheEntry(address).DataBlk);
-    sequencer.readCallback(address, getL1CacheEntry(address).DataBlk);
-  }
-
-  action(x_external_load_hit, "x", desc="Notify sequencer the load completed.") {
-    peek(responseIntraChipL1Network_in, ResponseMsg) {
-      sequencer.readCallback(address, getL1CacheEntry(address).DataBlk, getNondirectHitMachType(in_msg.Address, in_msg.Sender), PrefetchBit:No);
-    }
-  }
-
-
-  action(hh_store_hit, "\h", desc="If not prefetch, notify sequencer that store completed.") {
-    sequencer.writeCallback(address, getL1CacheEntry(address).DataBlk);
-    getL1CacheEntry(address).Dirty := true;
-  }
-
-  action(xx_external_store_hit, "\x", desc="Notify sequencer that store completed.") {
-    peek(responseIntraChipL1Network_in, ResponseMsg) {
-      sequencer.writeCallback(address, getL1CacheEntry(address).DataBlk, getNondirectHitMachType(in_msg.Address, in_msg.Sender), PrefetchBit:No);
-    }
-    getL1CacheEntry(address).Dirty := true;
-  }
-
-
-  action(i_allocateTBE, "i", desc="Allocate TBE (isPrefetch=0, number of invalidates=0)") {
-    check_allocate(L1_TBEs);
-    L1_TBEs.allocate(address);
-    L1_TBEs[address].isPrefetch := false;
-    L1_TBEs[address].Dirty := getL1CacheEntry(address).Dirty;
-    L1_TBEs[address].DataBlk := getL1CacheEntry(address).DataBlk;
-  }
-
-  action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") {
-    mandatoryQueue_in.dequeue();
-  }
-
-  action(l_popRequestQueue, "l", desc="Pop incoming request queue and profile the delay within this virtual network") {
-    profileMsgDelay(2, requestIntraChipL1Network_in.dequeue_getDelayCycles());
-  }
-
-  action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue and profile the delay within this virtual network") {
-    profileMsgDelay(3, responseIntraChipL1Network_in.dequeue_getDelayCycles());
-  }
-
-  action(s_deallocateTBE, "s", desc="Deallocate TBE") {
-    L1_TBEs.deallocate(address);
-  }
-
-  action(u_writeDataToL1Cache, "u", desc="Write data to cache") {
-    peek(responseIntraChipL1Network_in, ResponseMsg) {
-      getL1CacheEntry(address).DataBlk := in_msg.DataBlk;
-      getL1CacheEntry(address).Dirty := in_msg.Dirty;
-    }
-  }
-
-  action(q_updateAckCount, "q", desc="Update ack count") {
-    peek(responseIntraChipL1Network_in, ResponseMsg) {
-      L1_TBEs[address].pendingAcks := L1_TBEs[address].pendingAcks - in_msg.AckCount;
-      APPEND_TRANSITION_COMMENT(in_msg.AckCount);
-      APPEND_TRANSITION_COMMENT(" p: ");
-      APPEND_TRANSITION_COMMENT(L1_TBEs[address].pendingAcks);
-    }
-  }
-
-  action(z_stall, "z", desc="Stall") {
-  }
-
-  action(ff_deallocateL1CacheBlock, "\f", desc="Deallocate L1 cache block.  Sets the cache to not present, allowing a replacement in parallel with a fetch.") {
-    if (L1DcacheMemory.isTagPresent(address)) {
-      L1DcacheMemory.deallocate(address);
-    } else {
-      L1IcacheMemory.deallocate(address);
-    }
-  }
-
-  action(oo_allocateL1DCacheBlock, "\o", desc="Set L1 D-cache tag equal to tag of block B.") {
-    if (L1DcacheMemory.isTagPresent(address) == false) {
-      L1DcacheMemory.allocate(address);
-    }
-  }
-
-  action(pp_allocateL1ICacheBlock, "\p", desc="Set L1 I-cache tag equal to tag of block B.") {
-    if (L1IcacheMemory.isTagPresent(address) == false) {
-      L1IcacheMemory.allocate(address);
-    }
-  }
-
-  action(zz_recycleRequestQueue, "zz", desc="recycle L1 request queue") {
-    requestIntraChipL1Network_in.recycle();
-  }
-
-  action(z_recycleMandatoryQueue, "\z", desc="recycle L1 request queue") {
-    mandatoryQueue_in.recycle();
-  }
-
-
-  //*****************************************************
-  // TRANSITIONS
-  //*****************************************************
-
-  // Transitions for Load/Store/Replacement/WriteBack from transient states
-  transition({IS, IM, IS_I, M_I, E_I, SM}, {Load, Ifetch, Store, L1_Replacement}) {
-    z_recycleMandatoryQueue;
-  }
-
-  // Transitions from Idle
-  transition({NP,I}, L1_Replacement) {
-    ff_deallocateL1CacheBlock;
-  }
-
-  transition({NP,I}, Load, IS) {
-    oo_allocateL1DCacheBlock;
-    i_allocateTBE;
-    a_issueGETS;
-    k_popMandatoryQueue;
-  }
-
-  transition({NP,I}, Ifetch, IS) {
-    pp_allocateL1ICacheBlock;
-    i_allocateTBE;
-    ai_issueGETINSTR;
-    k_popMandatoryQueue;
-  }
-
-  transition({NP,I}, Store, IM) {
-    oo_allocateL1DCacheBlock;
-    i_allocateTBE;
-    b_issueGETX;
-    k_popMandatoryQueue;
-  }
-
-  transition({NP, I}, Inv) {
-    fi_sendInvAck;
-    l_popRequestQueue;
-  }
-
-  // Transitions from Shared
-  transition(S, {Load,Ifetch}) {
-    h_load_hit;
-    k_popMandatoryQueue;
-  }
-
-  transition(S, Store, SM) {
-    i_allocateTBE;
-    c_issueUPGRADE;
-    k_popMandatoryQueue;
-  }
-
-  transition(S, L1_Replacement, I) {
-    ff_deallocateL1CacheBlock;
-  }
-
-  transition(S, Inv, I) {
-    fi_sendInvAck;
-    l_popRequestQueue;
-  }
-
-  // Transitions from Exclusive
-
-  transition(E, {Load, Ifetch}) {
-    h_load_hit;
-    k_popMandatoryQueue;
-  }
-
-  transition(E, Store, M) {
-    hh_store_hit;
-    k_popMandatoryQueue;
-  }
-
-  transition(E, L1_Replacement, M_I) {
-    // silent E replacement??
-    i_allocateTBE;
-    g_issuePUTX;   // send data, but hold in case forwarded request
-    ff_deallocateL1CacheBlock;
-  }
-
-  transition(E, Inv, I) {
-    // don't send data
-    fi_sendInvAck;
-    l_popRequestQueue;
-  }
-
-  transition(E, Fwd_GETX, I) {
-    d_sendDataToRequestor;
-    l_popRequestQueue;
-  }
-
-  transition(E, {Fwd_GETS, Fwd_GET_INSTR}, S) {
-    d_sendDataToRequestor;
-    d2_sendDataToL2;
-    l_popRequestQueue;
-  }
-
-  // Transitions from Modified
-  transition(M, {Load, Ifetch}) {
-    h_load_hit;
-    k_popMandatoryQueue;
-  }
-
-  transition(M, Store) {
-    hh_store_hit;
-    k_popMandatoryQueue;
-  }
-
-  transition(M, L1_Replacement, M_I) {
-    i_allocateTBE;
-    g_issuePUTX;   // send data, but hold in case forwarded request
-    ff_deallocateL1CacheBlock;
-  }
-
-  transition(M_I, WB_Ack, I) {
-    s_deallocateTBE;
-    o_popIncomingResponseQueue;
-  }
-
-  transition(M, Inv, I) {
-    f_sendDataToL2;
-    l_popRequestQueue;
-  }
-
-  transition(M_I, Inv, I) {
-    ft_sendDataToL2_fromTBE;
-    s_deallocateTBE;
-    l_popRequestQueue;
-  }
-
-  transition(M, Fwd_GETX, I) {
-    d_sendDataToRequestor;
-    l_popRequestQueue;
-  }
-
-  transition(M, {Fwd_GETS, Fwd_GET_INSTR}, S) {
-    d_sendDataToRequestor;
-    d2_sendDataToL2;
-    l_popRequestQueue;
-  }
-
-  transition(M_I, Fwd_GETX, I) {
-    dt_sendDataToRequestor_fromTBE;
-    s_deallocateTBE;
-    l_popRequestQueue;
-  }
-
-  transition(M_I, {Fwd_GETS, Fwd_GET_INSTR}, I) {
-    dt_sendDataToRequestor_fromTBE;
-    d2t_sendDataToL2_fromTBE;
-    s_deallocateTBE;
-    l_popRequestQueue;
-  }
-
-  // Transitions from IS
-  transition({IS, IS_I}, Inv, IS_I) {
-    fi_sendInvAck;
-    l_popRequestQueue;
-  }
-
-  transition(IS, Data_all_Acks, S) {
-    u_writeDataToL1Cache;
-    x_external_load_hit;
-    s_deallocateTBE;
-    j_sendUnblock;
-    o_popIncomingResponseQueue;
-  }
-
-  transition(IS_I, Data_all_Acks, I) {
-    u_writeDataToL1Cache;
-    x_external_load_hit;
-    s_deallocateTBE;
-    j_sendUnblock;
-    o_popIncomingResponseQueue;
-  }
-
-
-  transition(IS, DataS_fromL1, S) {
-    u_writeDataToL1Cache;
-    j_sendUnblock;
-    x_external_load_hit;
-    s_deallocateTBE;
-    o_popIncomingResponseQueue;
-  }
-
-  transition(IS_I, DataS_fromL1, I) {
-    u_writeDataToL1Cache;
-    j_sendUnblock;
-    x_external_load_hit;
-    s_deallocateTBE;
-    o_popIncomingResponseQueue;
-  }
-
-  // directory is blocked when sending exclusive data
-  transition(IS_I, Data_Exclusive, E) {
-    u_writeDataToL1Cache;
-    x_external_load_hit;
-    jj_sendExclusiveUnblock;
-    s_deallocateTBE;
-    o_popIncomingResponseQueue;
-  }
-
-  transition(IS, Data_Exclusive, E) {
-    u_writeDataToL1Cache;
-    x_external_load_hit;
-    jj_sendExclusiveUnblock;
-    s_deallocateTBE;
-    o_popIncomingResponseQueue;
-  }
-
-  // Transitions from IM
-  transition({IM, SM}, Inv, IM) {
-    fi_sendInvAck;
-    l_popRequestQueue;
-  }
-
-  transition(IM, Data, SM) {
-    u_writeDataToL1Cache;
-    q_updateAckCount;
-    o_popIncomingResponseQueue;
-  }
-
-  transition(IM, Data_all_Acks, M) {
-    u_writeDataToL1Cache;
-    xx_external_store_hit;
-    jj_sendExclusiveUnblock;
-    s_deallocateTBE;
-    o_popIncomingResponseQueue;
-  }
-
-  // transitions from SM
-  transition({SM, IM}, Ack) {
-    q_updateAckCount;
-    o_popIncomingResponseQueue;
-  }
-
-  transition(SM, Ack_all, M) {
-    jj_sendExclusiveUnblock;
-    xx_external_store_hit;
-    s_deallocateTBE;
-    o_popIncomingResponseQueue;
-  }
-}
-
-
-