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author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-09-01 16:55:47 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-09-01 16:55:47 -0500 |
commit | 7a0d5aafe4b845a2d1cff6210d7c6ee66e8aba61 (patch) | |
tree | 6ef6157a33d226688f2909998b71936976ee755b /src/mem/protocol/MESI_Three_Level-L1cache.sm | |
parent | 00286fc5cbb7b8635d56eb335fed11d1499e2552 (diff) | |
download | gem5-7a0d5aafe4b845a2d1cff6210d7c6ee66e8aba61.tar.xz |
ruby: message buffers: significant changes
This patch is the final patch in a series of patches. The aim of the series
is to make ruby more configurable than it was. More specifically, the
connections between controllers are not at all possible (unless one is ready
to make significant changes to the coherence protocol). Moreover the buffers
themselves are magically connected to the network inside the slicc code.
These connections are not part of the configuration file.
This patch makes changes so that these connections will now be made in the
python configuration files associated with the protocols. This requires
each state machine to expose the message buffers it uses for input and output.
So, the patch makes these buffers configurable members of the machines.
The patch drops the slicc code that usd to connect these buffers to the
network. Now these buffers are exposed to the python configuration system
as Master and Slave ports. In the configuration files, any master port
can be connected any slave port. The file pyobject.cc has been modified to
take care of allocating the actual message buffer. This is inline with how
other port connections work.
Diffstat (limited to 'src/mem/protocol/MESI_Three_Level-L1cache.sm')
-rw-r--r-- | src/mem/protocol/MESI_Three_Level-L1cache.sm | 42 |
1 files changed, 23 insertions, 19 deletions
diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm index 170599a51..59249d822 100644 --- a/src/mem/protocol/MESI_Three_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm @@ -32,26 +32,30 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") Cycles l1_request_latency := 2; Cycles l1_response_latency := 2; Cycles to_l2_latency := 1; -{ - // From this node's L1 cache TO the network - // a local L1 -> this L2 bank, currently ordered with directory forwarded requests - MessageBuffer requestToL2, network="To", virtual_network="0", ordered="false", vnet_type="request"; - // a local L1 -> this L2 bank - MessageBuffer responseToL2, network="To", virtual_network="1", ordered="false", vnet_type="response"; - MessageBuffer unblockToL2, network="To", virtual_network="2", ordered="false", vnet_type="unblock"; - - // To this node's L1 cache FROM the network - // a L2 bank -> this L1 - MessageBuffer requestFromL2, network="From", virtual_network="0", ordered="false", vnet_type="request"; - // a L2 bank -> this L1 - MessageBuffer responseFromL2, network="From", virtual_network="1", ordered="false", vnet_type="response"; - - // Message Buffers between the L1 and the L0 Cache - // From the L1 cache to the L0 cache - MessageBuffer bufferToL0, network="To", physical_network="0", ordered="true"; - // From the L0 cache to the L1 cache - MessageBuffer bufferFromL0, network="From", physical_network="0", ordered="true"; + // Message Buffers between the L1 and the L0 Cache + // From the L1 cache to the L0 cache + MessageBuffer * bufferToL0, network="To", ordered="true"; + + // From the L0 cache to the L1 cache + MessageBuffer * bufferFromL0, network="From", ordered="true"; + + // Message queue from this L1 cache TO the network / L2 + MessageBuffer * requestToL2, network="To", virtual_network="0", + ordered="false", vnet_type="request"; + + MessageBuffer * responseToL2, network="To", virtual_network="1", + ordered="false", vnet_type="response"; + MessageBuffer * unblockToL2, network="To", virtual_network="2", + ordered="false", vnet_type="unblock"; + + // To this L1 cache FROM the network / L2 + MessageBuffer * requestFromL2, network="From", virtual_network="2", + ordered="false", vnet_type="request"; + MessageBuffer * responseFromL2, network="From", virtual_network="1", + ordered="false", vnet_type="response"; + +{ // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { // Base states |