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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-05 09:35:31 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-05 09:35:31 -0500 |
| commit | 8f29298bc7a9aee1572ba3de66ed12db5995509c (patch) | |
| tree | 371f920e41d5fda297bb55b8bb4b16df66ec5b05 /src/mem/protocol/MESI_Two_Level-L1cache.sm | |
| parent | abcc67010ed158b55b83e76e9092cae274a4975a (diff) | |
| download | gem5-8f29298bc7a9aee1572ba3de66ed12db5995509c.tar.xz | |
ruby: adds set and way indices to AbstractCacheEntry
Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-L1cache.sm')
0 files changed, 0 insertions, 0 deletions