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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-05 09:34:24 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-05 09:34:24 -0500 |
| commit | 7962a81148b5b38a32e12c4706ecb332c670e09b (patch) | |
| tree | 11ef35d7f7bc332e2d12fa4feb00da5e2c2c9f29 /src/mem/protocol/MESI_Two_Level-L1cache.sm | |
| parent | 419d437385f65d031769136851232550e5b1ba5e (diff) | |
| download | gem5-7962a81148b5b38a32e12c4706ecb332c670e09b.tar.xz | |
ruby: declare all protocol message buffers as parameters
MessageBuffer is a SimObject now. There were protocols that still declared
some of the message buffers are variables of the controller, but not as input
parameters. Special handling was required for these variables in the SLICC
compiler. This patch changes this. Now all message buffers are declared as
input parameters.
Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-L1cache.sm')
| -rw-r--r-- | src/mem/protocol/MESI_Two_Level-L1cache.sm | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm index 184f735c7..8033e5983 100644 --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm @@ -61,10 +61,13 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") // a L2 bank -> this L1 MessageBuffer * responseToL1Cache, network="From", virtual_network="1", vnet_type="response"; -{ + // Request Buffer for prefetches - MessageBuffer optionalQueue; + MessageBuffer * optionalQueue; + // Buffer for requests generated by the processor core. + MessageBuffer * mandatoryQueue; +{ // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { // Base states @@ -151,8 +154,6 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") TBETable TBEs, template="<L1Cache_TBE>", constructor="m_number_of_TBEs"; - MessageBuffer mandatoryQueue; - int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; void set_cache_entry(AbstractCacheEntry a); |