diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-09-01 16:55:47 -0500 |
---|---|---|
committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-09-01 16:55:47 -0500 |
commit | 7a0d5aafe4b845a2d1cff6210d7c6ee66e8aba61 (patch) | |
tree | 6ef6157a33d226688f2909998b71936976ee755b /src/mem/protocol/MESI_Two_Level-L1cache.sm | |
parent | 00286fc5cbb7b8635d56eb335fed11d1499e2552 (diff) | |
download | gem5-7a0d5aafe4b845a2d1cff6210d7c6ee66e8aba61.tar.xz |
ruby: message buffers: significant changes
This patch is the final patch in a series of patches. The aim of the series
is to make ruby more configurable than it was. More specifically, the
connections between controllers are not at all possible (unless one is ready
to make significant changes to the coherence protocol). Moreover the buffers
themselves are magically connected to the network inside the slicc code.
These connections are not part of the configuration file.
This patch makes changes so that these connections will now be made in the
python configuration files associated with the protocols. This requires
each state machine to expose the message buffers it uses for input and output.
So, the patch makes these buffers configurable members of the machines.
The patch drops the slicc code that usd to connect these buffers to the
network. Now these buffers are exposed to the python configuration system
as Master and Slave ports. In the configuration files, any master port
can be connected any slave port. The file pyobject.cc has been modified to
take care of allocating the actual message buffer. This is inline with how
other port connections work.
Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-L1cache.sm')
-rw-r--r-- | src/mem/protocol/MESI_Two_Level-L1cache.sm | 39 |
1 files changed, 24 insertions, 15 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm index 96c1699b7..6c98c23e9 100644 --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm @@ -37,25 +37,34 @@ machine(L1Cache, "MESI Directory L1 Cache CMP") Cycles to_l2_latency := 1; bool send_evictions; bool enable_prefetch := "False"; + + // Message Queues + // From this node's L1 cache TO the network + + // a local L1 -> this L2 bank, currently ordered with directory forwarded requests + MessageBuffer * requestFromL1Cache, network="To", virtual_network="0", + ordered="false", vnet_type="request"; + + // a local L1 -> this L2 bank + MessageBuffer * responseFromL1Cache, network="To", virtual_network="1", + ordered="false", vnet_type="response"; + + MessageBuffer * unblockFromL1Cache, network="To", virtual_network="2", + ordered="false", vnet_type="unblock"; + + + // To this node's L1 cache FROM the network + // a L2 bank -> this L1 + MessageBuffer * requestToL1Cache, network="From", virtual_network="2", + ordered="false", vnet_type="request"; + + // a L2 bank -> this L1 + MessageBuffer * responseToL1Cache, network="From", virtual_network="1", + ordered="false", vnet_type="response"; { - // NODE L1 CACHE - // From this node's L1 cache TO the network - // a local L1 -> this L2 bank, currently ordered with directory forwarded requests - MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false", vnet_type="request"; - // a local L1 -> this L2 bank - MessageBuffer responseFromL1Cache, network="To", virtual_network="1", ordered="false", vnet_type="response"; - MessageBuffer unblockFromL1Cache, network="To", virtual_network="2", ordered="false", vnet_type="unblock"; - - - // To this node's L1 cache FROM the network - // a L2 bank -> this L1 - MessageBuffer requestToL1Cache, network="From", virtual_network="0", ordered="false", vnet_type="request"; - // a L2 bank -> this L1 - MessageBuffer responseToL1Cache, network="From", virtual_network="1", ordered="false", vnet_type="response"; // Request Buffer for prefetches MessageBuffer optionalQueue, ordered="false"; - // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { // Base states |