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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-03-13 18:19:08 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-06-13 15:52:32 +0000 |
| commit | 12db50c89584938839e035da47d206250cbfd7c2 (patch) | |
| tree | 831a4151b29cdc14958b8dab2cce97fc3136d7b6 /src/mem/protocol/MESI_Two_Level-L2cache.sm | |
| parent | dd3fc1f996679f4cfd29f980d43a0652542e6d9b (diff) | |
| download | gem5-12db50c89584938839e035da47d206250cbfd7c2.tar.xz | |
ruby: Add support for address ranges in the directory
Previously the directory covered a flat address range that always
started from address 0. This change adds a vector of address ranges
with interleaving and hashing that each directory keeps track of and
the necessary flexibility to support systems with non continuous
memory ranges.
Change-Id: I6ea1c629bdf4c5137b7d9c89dbaf6c826adfd977
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2903
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-L2cache.sm')
| -rw-r--r-- | src/mem/protocol/MESI_Two_Level-L2cache.sm | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm index d7a88c199..5a8cfae6d 100644 --- a/src/mem/protocol/MESI_Two_Level-L2cache.sm +++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm @@ -158,6 +158,7 @@ machine(MachineType:L2Cache, "MESI Directory L2 Cache CMP") void unset_tbe(); void wakeUpBuffers(Addr a); void profileMsgDelay(int virtualNetworkType, Cycles c); + MachineID mapAddressToMachine(Addr addr, MachineType mtype); // inclusive cache, returns L2 entries only Entry getCacheEntry(Addr addr), return_by_pointer="yes" { @@ -400,7 +401,7 @@ machine(MachineType:L2Cache, "MESI Directory L2 Cache CMP") out_msg.addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.MessageSize := MessageSizeType:Control; } } @@ -425,7 +426,7 @@ machine(MachineType:L2Cache, "MESI Directory L2 Cache CMP") out_msg.addr := address; out_msg.Type := CoherenceResponseType:MEMORY_DATA; out_msg.Sender := machineID; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.DataBlk := cache_entry.DataBlk; out_msg.Dirty := cache_entry.Dirty; out_msg.MessageSize := MessageSizeType:Response_Data; @@ -437,7 +438,7 @@ machine(MachineType:L2Cache, "MESI Directory L2 Cache CMP") out_msg.addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.MessageSize := MessageSizeType:Response_Control; } } @@ -448,7 +449,7 @@ machine(MachineType:L2Cache, "MESI Directory L2 Cache CMP") out_msg.addr := address; out_msg.Type := CoherenceResponseType:MEMORY_DATA; out_msg.Sender := machineID; - out_msg.Destination.add(map_Address_to_Directory(address)); + out_msg.Destination.add(mapAddressToMachine(address, MachineType:Directory)); out_msg.DataBlk := tbe.DataBlk; out_msg.Dirty := tbe.Dirty; out_msg.MessageSize := MessageSizeType:Response_Data; |