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| author | Gabe Black <gabeblack@google.com> | 2018-01-08 19:08:17 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2018-01-11 09:34:40 +0000 |
| commit | f3d4d6f2028684a85096d5023ba0f106438c1b5e (patch) | |
| tree | 1243ab13104e74696b0d6f3ed42f8b4730179b57 /src/mem/protocol/MESI_Two_Level-dir.sm | |
| parent | f96e542dd88762556bda357fe046318ccf31268f (diff) | |
| download | gem5-f3d4d6f2028684a85096d5023ba0f106438c1b5e.tar.xz | |
cpu: Make the CPU's TLB parameter a BaseTLB.
This is instead of the architecture specific version.
Change-Id: I906ec16eee1f65f0e9b9c24b401430f9ea01637b
Reviewed-on: https://gem5-review.googlesource.com/7349
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-dir.sm')
0 files changed, 0 insertions, 0 deletions