ruby: rename variables Addr to addr

Avoid clash between type Addr and variable name Addr.

1 files changed, 18 insertions, 18 deletions

diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/protocol/MESI_Two_Level-dir.sm
index 142c073c3..e213cf060 100644
--- a/src/mem/protocol/MESI_Two_Level-dir.sm
+++ b/src/mem/protocol/MESI_Two_Level-dir.sm
@@ -194,13 +194,13 @@ machine(Directory, "MESI Two Level directory protocol")
       peek(requestNetwork_in, RequestMsg) {
         assert(in_msg.Destination.isElement(machineID));
         if (isGETRequest(in_msg.Type)) {
-          trigger(Event:Fetch, in_msg.Addr, TBEs[in_msg.Addr]);
+          trigger(Event:Fetch, in_msg.addr, TBEs[in_msg.addr]);
         } else if (in_msg.Type == CoherenceRequestType:DMA_READ) {
-          trigger(Event:DMA_READ, makeLineAddress(in_msg.Addr),
-                  TBEs[makeLineAddress(in_msg.Addr)]);
+          trigger(Event:DMA_READ, makeLineAddress(in_msg.addr),
+                  TBEs[makeLineAddress(in_msg.addr)]);
         } else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) {
-          trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Addr),
-                  TBEs[makeLineAddress(in_msg.Addr)]);
+          trigger(Event:DMA_WRITE, makeLineAddress(in_msg.addr),
+                  TBEs[makeLineAddress(in_msg.addr)]);
         } else {
           DPRINTF(RubySlicc, "%s\n", in_msg);
           error("Invalid message");
@@ -214,9 +214,9 @@ machine(Directory, "MESI Two Level directory protocol")
       peek(responseNetwork_in, ResponseMsg) {
         assert(in_msg.Destination.isElement(machineID));
         if (in_msg.Type == CoherenceResponseType:MEMORY_DATA) {
-          trigger(Event:Data, in_msg.Addr, TBEs[in_msg.Addr]);
+          trigger(Event:Data, in_msg.addr, TBEs[in_msg.addr]);
         } else if (in_msg.Type == CoherenceResponseType:ACK) {
-          trigger(Event:CleanReplacement, in_msg.Addr, TBEs[in_msg.Addr]);
+          trigger(Event:CleanReplacement, in_msg.addr, TBEs[in_msg.addr]);
         } else {
           DPRINTF(RubySlicc, "%s\n", in_msg.Type);
           error("Invalid message");
@@ -230,9 +230,9 @@ machine(Directory, "MESI Two Level directory protocol")
     if (memQueue_in.isReady()) {
       peek(memQueue_in, MemoryMsg) {
         if (in_msg.Type == MemoryRequestType:MEMORY_READ) {
-          trigger(Event:Memory_Data, in_msg.Addr, TBEs[in_msg.Addr]);
+          trigger(Event:Memory_Data, in_msg.addr, TBEs[in_msg.addr]);
         } else if (in_msg.Type == MemoryRequestType:MEMORY_WB) {
-          trigger(Event:Memory_Ack, in_msg.Addr, TBEs[in_msg.Addr]);
+          trigger(Event:Memory_Ack, in_msg.addr, TBEs[in_msg.addr]);
         } else {
           DPRINTF(RubySlicc, "%s\n", in_msg.Type);
           error("Invalid message");
@@ -246,7 +246,7 @@ machine(Directory, "MESI Two Level directory protocol")
   action(a_sendAck, "a", desc="Send ack to L2") {
     peek(responseNetwork_in, ResponseMsg) {
       enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) {
-        out_msg.Addr := address;
+        out_msg.addr := address;
         out_msg.Type := CoherenceResponseType:MEMORY_ACK;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Sender);
@@ -258,7 +258,7 @@ machine(Directory, "MESI Two Level directory protocol")
   action(d_sendData, "d", desc="Send data to requestor") {
     peek(memQueue_in, MemoryMsg) {
       enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) {
-        out_msg.Addr := address;
+        out_msg.addr := address;
         out_msg.Type := CoherenceResponseType:MEMORY_DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
@@ -266,7 +266,7 @@ machine(Directory, "MESI Two Level directory protocol")
         out_msg.Dirty := false;
         out_msg.MessageSize := MessageSizeType:Response_Data;
 
-        Entry e := getDirectoryEntry(in_msg.Addr);
+        Entry e := getDirectoryEntry(in_msg.addr);
         e.Owner := in_msg.OriginalRequestorMachId;
       }
     }
@@ -276,7 +276,7 @@ machine(Directory, "MESI Two Level directory protocol")
   action(aa_sendAck, "aa", desc="Send ack to L2") {
     peek(memQueue_in, MemoryMsg) {
       enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) {
-        out_msg.Addr := address;
+        out_msg.addr := address;
         out_msg.Type := CoherenceResponseType:MEMORY_ACK;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.OriginalRequestorMachId);
@@ -328,7 +328,7 @@ machine(Directory, "MESI Two Level directory protocol")
   action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") {
     peek(memQueue_in, MemoryMsg) {
       enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) {
-        out_msg.Addr := address;
+        out_msg.addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.DataBlk := in_msg.DataBlk;   // we send the entire data block and rely on the dma controller to split it up if need be
         out_msg.Destination.add(map_Address_to_DMA(address));
@@ -347,7 +347,7 @@ machine(Directory, "MESI Two Level directory protocol")
 
   action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
       enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) {
-        out_msg.Addr := address;
+        out_msg.addr := address;
         out_msg.Type := CoherenceResponseType:ACK;
         out_msg.Destination.add(map_Address_to_DMA(address));
         out_msg.MessageSize := MessageSizeType:Writeback_Control;
@@ -365,7 +365,7 @@ machine(Directory, "MESI Two Level directory protocol")
   action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") {
     peek(requestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, directory_latency) {
-        out_msg.Addr := address;
+        out_msg.addr := address;
         out_msg.Type := CoherenceResponseType:INV;
         out_msg.Sender := machineID;
         out_msg.Destination.add(getDirectoryEntry(address).Owner);
@@ -378,7 +378,7 @@ machine(Directory, "MESI Two Level directory protocol")
   action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") {
     peek(responseNetwork_in, ResponseMsg) {
       enqueue(responseNetwork_out, ResponseMsg, to_mem_ctrl_latency) {
-        out_msg.Addr := address;
+        out_msg.addr := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.DataBlk := in_msg.DataBlk;   // we send the entire data block and rely on the dma controller to split it up if need be
         out_msg.Destination.add(map_Address_to_DMA(address));
@@ -392,7 +392,7 @@ machine(Directory, "MESI Two Level directory protocol")
       TBEs.allocate(address);
       set_tbe(TBEs[address]);
       tbe.DataBlk := in_msg.DataBlk;
-      tbe.PhysicalAddress := in_msg.Addr;
+      tbe.PhysicalAddress := in_msg.addr;
       tbe.Len := in_msg.Len;
     }
   }