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author | Iru Cai <mytbk920423@gmail.com> | 2019-02-28 17:07:16 +0800 |
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committer | Iru Cai <mytbk920423@gmail.com> | 2019-03-20 16:08:09 +0800 |
commit | 0ca254aa8381ba2fae61a4a056301e35da9ffab3 (patch) | |
tree | 612664055ade4cca58186a76fee4dd7522aeb305 /src/mem/protocol/MESI_Two_Level-msg.sm | |
parent | 476fd104a80095207eec0b594baa642937fbac01 (diff) | |
download | gem5-0ca254aa8381ba2fae61a4a056301e35da9ffab3.tar.xz |
invisispec-1.0 source
Diffstat (limited to 'src/mem/protocol/MESI_Two_Level-msg.sm')
-rw-r--r-- | src/mem/protocol/MESI_Two_Level-msg.sm | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/mem/protocol/MESI_Two_Level-msg.sm b/src/mem/protocol/MESI_Two_Level-msg.sm index 738019e7b..d4269193d 100644 --- a/src/mem/protocol/MESI_Two_Level-msg.sm +++ b/src/mem/protocol/MESI_Two_Level-msg.sm @@ -36,6 +36,8 @@ enumeration(CoherenceRequestType, desc="...") { GET_INSTR, desc="Get Instruction"; INV, desc="INValidate"; PUTX, desc="Replacement message"; + GETSPEC, desc="Get Speculatively"; + EXPOSE, desc="Expose"; WB_ACK, desc="Writeback ack"; @@ -68,7 +70,9 @@ structure(RequestMsg, desc="...", interface="Message") { int Len; bool Dirty, default="false", desc="Dirty bit"; PrefetchBit Prefetch, desc="Is this a prefetch request"; - + MachineID origin; + int idx, default="-1", desc="LQ index"; + bool functionalRead(Packet *pkt) { // Only PUTX messages contains the data block if (Type == CoherenceRequestType:PUTX) { |