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authorNilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E) <nilay@cs.wisc.edu>2013-05-21 11:31:31 -0500
committerNilay Vaish ext:(%2C%20Malek%20Musleh%20%3Cmalek.musleh%40gmail.com%3E) <nilay@cs.wisc.edu>2013-05-21 11:31:31 -0500
commit59a7abff29aa5a687e1693f003c20d7e2000c40a (patch)
treee1cf2cf822cf5b1002a6b72d8d613f65e0e1df8d /src/mem/protocol/MI_example-cache.sm
parentd3c33d91b68e917478dba48c03a674b21ebd2747 (diff)
downloadgem5-59a7abff29aa5a687e1693f003c20d7e2000c40a.tar.xz
ruby: add stats to .sm files, remove cache profiler
This patch changes the way cache statistics are collected in ruby. As of now, there is separate entity called CacheProfiler which holds statistical variables for caches. The CacheMemory class defines different functions for accessing the CacheProfiler. These functions are then invoked in the .sm files. I find this approach opaque and prone to error. Secondly, we probably should not be paying the cost of a function call for recording statistics. Instead, this patch allows for accessing statistical variables in the .sm files. The collection would become transparent. Secondly, it would happen in place, so no function calls. The patch also removes the CacheProfiler class. --HG-- rename : src/mem/slicc/ast/InfixOperatorExprAST.py => src/mem/slicc/ast/OperatorExprAST.py
Diffstat (limited to 'src/mem/protocol/MI_example-cache.sm')
-rw-r--r--src/mem/protocol/MI_example-cache.sm12
1 files changed, 8 insertions, 4 deletions
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index f0bd7b99e..a0a23c308 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -335,10 +335,12 @@ machine(L1Cache, "MI Example L1 Cache")
profileMsgDelay(2, forwardRequestNetwork_in.dequeue_getDelayCycles());
}
- action(p_profileMiss, "p", desc="Profile cache miss") {
- peek(mandatoryQueue_in, RubyRequest) {
- cacheMemory.profileMiss(in_msg);
- }
+ action(p_profileMiss, "pi", desc="Profile cache miss") {
+ ++cacheMemory.demand_misses;
+ }
+
+ action(p_profileHit, "ph", desc="Profile cache miss") {
+ ++cacheMemory.demand_hits;
}
action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
@@ -427,11 +429,13 @@ machine(L1Cache, "MI Example L1 Cache")
transition(M, Store) {
s_store_hit;
+ p_profileHit;
m_popMandatoryQueue;
}
transition(M, {Load, Ifetch}) {
r_load_hit;
+ p_profileHit;
m_popMandatoryQueue;
}