Change interface between coherence protocols and CacheMemory

The purpose of this patch is to change the way CacheMemory interfaces with
coherence protocols. Currently, whenever a cache controller (defined in the
protocol under consideration) needs to carry out any operation on a cache
block, it looks up the tag hash map and figures out whether or not the block
exists in the cache. In case it does exist, the operation is carried out
(which requires another lookup). As observed through profiling of different
protocols, multiple such lookups take place for a given cache block. It was
noted that the tag lookup takes anything from 10% to 20% of the simulation
time. In order to reduce this time, this patch is being posted.

I have to acknowledge that the many of the thoughts that went in to this
patch belong to Brad.

Changes to CacheMemory, TBETable and AbstractCacheEntry classes:
1. The lookup function belonging to CacheMemory class now returns a pointer
to a cache block entry, instead of a reference. The pointer is NULL in case
the block being looked up is not present in the cache. Similar change has
been carried out in the lookup function of the TBETable class.
2. Function for setting and getting access permission of a cache block have
been moved from CacheMemory class to AbstractCacheEntry class.
3. The allocate function in CacheMemory class now returns pointer to the
allocated cache entry.

Changes to SLICC:
1. Each action now has implicit variables - cache_entry and tbe. cache_entry,
if != NULL, must point to the cache entry for the address on which the action
is being carried out. Similarly, tbe should also point to the transaction
buffer entry of the address on which the action is being carried out.
2. If a cache entry or a transaction buffer entry is passed on as an
argument to a function, it is presumed that a pointer is being passed on.
3. The cache entry and the tbe pointers received __implicitly__ by the
actions, are passed __explicitly__ to the trigger function.
4. While performing an action, set/unset_cache_entry, set/unset_tbe are to
be used for setting / unsetting cache entry and tbe pointers respectively.
5. is_valid() and is_invalid() has been made available for testing whether
a given pointer 'is not NULL' and 'is NULL' respectively.
6. Local variables are now available, but they are assumed to be pointers
always.
7. It is now possible for an object of the derieved class to make calls to
a function defined in the interface.
8. An OOD token has been introduced in SLICC. It is same as the NULL token
used in C/C++. If you are wondering, OOD stands for Out Of Domain.
9. static_cast can now taken an optional parameter that asks for casting the
given variable to a pointer of the given type.
10. Functions can be annotated with 'return_by_pointer=yes' to return a
pointer.
11. StateMachine has two new variables, EntryType and TBEType. EntryType is
set to the type which inherits from 'AbstractCacheEntry'. There can only be
one such type in the machine. TBEType is set to the type for which 'TBE' is
used as the name.

All the protocols have been modified to conform with the new interface.

1 files changed, 70 insertions, 42 deletions

diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index 8232e93e1..96b7ab826 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -73,7 +73,15 @@ machine(L1Cache, "MI Example L1 Cache")
 
   TBETable TBEs, template_hack="<L1Cache_TBE>";
 
+  // PROTOTYPES
+  void set_cache_entry(AbstractCacheEntry a);
+  void unset_cache_entry();
+  void set_tbe(TBE b);
+  void unset_tbe();
 
+  Entry getCacheEntry(Address address), return_by_pointer="yes" {
+    return static_cast(Entry, "pointer", cacheMemory.lookup(address));
+  }
 
   // FUNCTIONS
   Event mandatory_request_type_to_event(CacheRequestType type) {
@@ -88,35 +96,31 @@ machine(L1Cache, "MI Example L1 Cache")
     }
   }
 
-  Entry getCacheEntry(Address addr), return_by_ref="yes" {
-    return static_cast(Entry, cacheMemory[addr]);
-  }
-
-  State getState(Address addr) {
+  State getState(TBE tbe, Entry cache_entry, Address addr) {
 
-    if (TBEs.isPresent(addr)) {
-      return TBEs[addr].TBEState;
+    if (is_valid(tbe)) {
+      return tbe.TBEState;
     }
-    else if (cacheMemory.isTagPresent(addr)) {
-      return getCacheEntry(addr).CacheState;
+    else if (is_valid(cache_entry)) {
+      return cache_entry.CacheState;
     }
     else {
       return State:I;
     }
   }
 
-  void setState(Address addr, State state) {
+  void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 
-    if (TBEs.isPresent(addr)) {
-      TBEs[addr].TBEState := state;
+    if (is_valid(tbe)) {
+      tbe.TBEState := state;
     }
 
-    if (cacheMemory.isTagPresent(addr)) {
-      getCacheEntry(addr).CacheState := state;
+    if (is_valid(cache_entry)) {
+      cache_entry.CacheState := state;
       if (state == State:M) {
-        cacheMemory.changePermission(addr, AccessPermission:Read_Write);
+        cache_entry.changePermission(AccessPermission:Read_Write);
       } else {
-        cacheMemory.changePermission(addr, AccessPermission:Invalid);
+        cache_entry.changePermission(AccessPermission:Invalid);
       }
     }
   }
@@ -141,17 +145,21 @@ machine(L1Cache, "MI Example L1 Cache")
   in_port(forwardRequestNetwork_in, RequestMsg, forwardToCache) {
     if (forwardRequestNetwork_in.isReady()) {
       peek(forwardRequestNetwork_in, RequestMsg, block_on="Address") {
+
+        Entry cache_entry := getCacheEntry(in_msg.Address);
+        TBE tbe := TBEs[in_msg.Address];
+
         if (in_msg.Type == CoherenceRequestType:GETX) {
-          trigger(Event:Fwd_GETX, in_msg.Address);
+          trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe);
         }
         else if (in_msg.Type == CoherenceRequestType:WB_ACK) {
-          trigger(Event:Writeback_Ack, in_msg.Address);
+          trigger(Event:Writeback_Ack, in_msg.Address, cache_entry, tbe);
         }
         else if (in_msg.Type == CoherenceRequestType:WB_NACK) {
-          trigger(Event:Writeback_Nack, in_msg.Address);
+          trigger(Event:Writeback_Nack, in_msg.Address, cache_entry, tbe);
         }
         else if (in_msg.Type == CoherenceRequestType:INV) {
-          trigger(Event:Inv, in_msg.Address);
+          trigger(Event:Inv, in_msg.Address, cache_entry, tbe);
         }
         else {
           error("Unexpected message");
@@ -163,8 +171,12 @@ machine(L1Cache, "MI Example L1 Cache")
   in_port(responseNetwork_in, ResponseMsg, responseToCache) {
     if (responseNetwork_in.isReady()) {
       peek(responseNetwork_in, ResponseMsg, block_on="Address") {
+
+        Entry cache_entry := getCacheEntry(in_msg.Address);
+        TBE tbe := TBEs[in_msg.Address];
+
         if (in_msg.Type == CoherenceResponseType:DATA) {
-          trigger(Event:Data, in_msg.Address);
+          trigger(Event:Data, in_msg.Address, cache_entry, tbe);
         }
         else {
           error("Unexpected message");
@@ -178,14 +190,17 @@ machine(L1Cache, "MI Example L1 Cache")
     if (mandatoryQueue_in.isReady()) {
       peek(mandatoryQueue_in, CacheMsg, block_on="LineAddress") {
 
-
-        if (cacheMemory.isTagPresent(in_msg.LineAddress) == false &&
+        Entry cache_entry := getCacheEntry(in_msg.LineAddress);
+        if (is_invalid(cache_entry) &&
             cacheMemory.cacheAvail(in_msg.LineAddress) == false ) {
           // make room for the block
-          trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.LineAddress));
+          trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.LineAddress),
+                  getCacheEntry(cacheMemory.cacheProbe(in_msg.LineAddress)),
+                  TBEs[cacheMemory.cacheProbe(in_msg.LineAddress)]);
         }
         else {
-          trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress);
+          trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress,
+                  cache_entry, TBEs[in_msg.LineAddress]);
         }
       }
     }
@@ -205,11 +220,12 @@ machine(L1Cache, "MI Example L1 Cache")
 
   action(b_issuePUT, "b", desc="Issue a PUT request") {
     enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) {
+      assert(is_valid(cache_entry));
       out_msg.Address := address;
       out_msg.Type := CoherenceRequestType:PUTX;
       out_msg.Requestor := machineID;
       out_msg.Destination.add(map_Address_to_Directory(address));
-      out_msg.DataBlk := getCacheEntry(address).DataBlk;
+      out_msg.DataBlk := cache_entry.DataBlk;
       out_msg.MessageSize := MessageSizeType:Data;
     }
   }
@@ -218,11 +234,12 @@ machine(L1Cache, "MI Example L1 Cache")
   action(e_sendData, "e", desc="Send data from cache to requestor") {
     peek(forwardRequestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
+        assert(is_valid(cache_entry));
         out_msg.Address := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
-        out_msg.DataBlk := getCacheEntry(address).DataBlk;
+        out_msg.DataBlk := cache_entry.DataBlk;
         out_msg.MessageSize := MessageSizeType:Response_Data;
       }
     }
@@ -231,26 +248,28 @@ machine(L1Cache, "MI Example L1 Cache")
   action(ee_sendDataFromTBE, "\e", desc="Send data from TBE to requestor") {
     peek(forwardRequestNetwork_in, RequestMsg) {
       enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) {
+        assert(is_valid(tbe));
         out_msg.Address := address;
         out_msg.Type := CoherenceResponseType:DATA;
         out_msg.Sender := machineID;
         out_msg.Destination.add(in_msg.Requestor);
-        out_msg.DataBlk := TBEs[address].DataBlk;
+        out_msg.DataBlk := tbe.DataBlk;
         out_msg.MessageSize := MessageSizeType:Response_Data;
       }
     }
   }
 
-
   action(i_allocateL1CacheBlock, "i", desc="Allocate a cache block") {
-    if (cacheMemory.isTagPresent(address) == false) {
-      cacheMemory.allocate(address, new Entry);
+    if (is_valid(cache_entry)) {
+    } else {
+      set_cache_entry(cacheMemory.allocate(address, new Entry));
     }
   }
 
   action(h_deallocateL1CacheBlock, "h", desc="deallocate a cache block") {
-    if (cacheMemory.isTagPresent(address) == true) {
+    if (is_valid(cache_entry)) {
       cacheMemory.deallocate(address);
+      unset_cache_entry();
     }
   }
 
@@ -273,55 +292,64 @@ machine(L1Cache, "MI Example L1 Cache")
   }
 
   action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
-    DPRINTF(RubySlicc,"%s\n", getCacheEntry(address).DataBlk);
+    assert(is_valid(cache_entry));
+    DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
     sequencer.readCallback(address, 
                            GenericMachineType:L1Cache,
-                           getCacheEntry(address).DataBlk);
+                           cache_entry.DataBlk);
   }
 
   action(rx_load_hit, "rx", desc="External load completed.") {
     peek(responseNetwork_in, ResponseMsg) {
-      DPRINTF(RubySlicc,"%s\n", getCacheEntry(address).DataBlk);
+      assert(is_valid(cache_entry));
+      DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
       sequencer.readCallback(address, 
                              getNondirectHitMachType(in_msg.Sender),
-                             getCacheEntry(address).DataBlk);
+                             cache_entry.DataBlk);
     }
   }
 
   action(s_store_hit, "s", desc="Notify sequencer that store completed.") {
-    DPRINTF(RubySlicc,"%s\n", getCacheEntry(address).DataBlk);
+    assert(is_valid(cache_entry));
+    DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
     sequencer.writeCallback(address, 
                             GenericMachineType:L1Cache,
-                            getCacheEntry(address).DataBlk);
+                            cache_entry.DataBlk);
   }
 
   action(sx_store_hit, "sx", desc="External store completed.") {
     peek(responseNetwork_in, ResponseMsg) {
-      DPRINTF(RubySlicc,"%s\n", getCacheEntry(address).DataBlk);
+      assert(is_valid(cache_entry));
+      DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk);
       sequencer.writeCallback(address, 
                               getNondirectHitMachType(in_msg.Sender),
-                              getCacheEntry(address).DataBlk);
+                              cache_entry.DataBlk);
     }
   }
 
   action(u_writeDataToCache, "u", desc="Write data to the cache") {
     peek(responseNetwork_in, ResponseMsg) {
-      getCacheEntry(address).DataBlk := in_msg.DataBlk;
+      assert(is_valid(cache_entry));
+      cache_entry.DataBlk := in_msg.DataBlk;
     }
   }
 
 
   action(v_allocateTBE, "v", desc="Allocate TBE") {
     TBEs.allocate(address);
+    set_tbe(TBEs[address]);
   }
 
 
   action(w_deallocateTBE, "w", desc="Deallocate TBE") {
     TBEs.deallocate(address);
+    unset_tbe();
   }
 
   action(x_copyDataFromCacheToTBE, "x", desc="Copy data from cache to TBE") {
-    TBEs[address].DataBlk := getCacheEntry(address).DataBlk;
+    assert(is_valid(cache_entry));
+    assert(is_valid(tbe));
+    tbe.DataBlk := cache_entry.DataBlk;
   }
 
   action(z_stall, "z", desc="stall") {