diff options
author | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-23 16:41:59 -0800 |
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committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2011-02-23 16:41:59 -0800 |
commit | 12a05c23b7d351afee4b0c531021d8fb8ea5f57d (patch) | |
tree | 99a18647ecf642166068187915f2816a1007567d /src/mem/protocol/MI_example-cache.sm | |
parent | 7842e955193c3fba850201acc45001306fe2ff9b (diff) | |
download | gem5-12a05c23b7d351afee4b0c531021d8fb8ea5f57d.tar.xz |
ruby: automate permission setting
This patch integrates permissions with cache and memory states, and then
automates the setting of permissions within the generated code. No longer
does one need to manually set the permissions within the setState funciton.
This patch will faciliate easier functional access support by always correctly
setting permissions for both cache and memory states.
--HG--
rename : src/mem/slicc/ast/EnumDeclAST.py => src/mem/slicc/ast/StateDeclAST.py
rename : src/mem/slicc/ast/TypeFieldEnumAST.py => src/mem/slicc/ast/TypeFieldStateAST.py
Diffstat (limited to 'src/mem/protocol/MI_example-cache.sm')
-rw-r--r-- | src/mem/protocol/MI_example-cache.sm | 21 |
1 files changed, 8 insertions, 13 deletions
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index 96b7ab826..26572770c 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -14,15 +14,15 @@ machine(L1Cache, "MI Example L1 Cache") MessageBuffer responseToCache, network="From", virtual_network="4", ordered="true"; // STATES - enumeration(State, desc="Cache states") { - I, desc="Not Present/Invalid"; - II, desc="Not Present/Invalid, issued PUT"; - M, desc="Modified"; - MI, desc="Modified, issued PUT"; - MII, desc="Modified, issued PUTX, received nack"; + state_declaration(State, desc="Cache states") { + I, AccessPermission:Invalid, desc="Not Present/Invalid"; + II, AccessPermission:Busy, desc="Not Present/Invalid, issued PUT"; + M, AccessPermission:Read_Write, desc="Modified"; + MI, AccessPermission:Busy, desc="Modified, issued PUT"; + MII, AccessPermission:Busy, desc="Modified, issued PUTX, received nack"; - IS, desc="Issued request for LOAD/IFETCH"; - IM, desc="Issued request for STORE/ATOMIC"; + IS, AccessPermission:Busy, desc="Issued request for LOAD/IFETCH"; + IM, AccessPermission:Busy, desc="Issued request for STORE/ATOMIC"; } // EVENTS @@ -117,11 +117,6 @@ machine(L1Cache, "MI Example L1 Cache") if (is_valid(cache_entry)) { cache_entry.CacheState := state; - if (state == State:M) { - cache_entry.changePermission(AccessPermission:Read_Write); - } else { - cache_entry.changePermission(AccessPermission:Invalid); - } } } |