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author | Lena Olson <lena@cs.wisc.edu> | 2013-06-18 16:58:33 -0500 |
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committer | Lena Olson <lena@cs.wisc.edu> | 2013-06-18 16:58:33 -0500 |
commit | 7c39d5df7ea61a39ad1b9a3aa70d22f0e2943b21 (patch) | |
tree | d2d2ca457dd5a1d43ee2389ce7202b68f567b951 /src/mem/protocol/MI_example-cache.sm | |
parent | d06064c38613662dfbf68a701052278b4018de8c (diff) | |
download | gem5-7c39d5df7ea61a39ad1b9a3aa70d22f0e2943b21.tar.xz |
ruby: restrict Address to being a type and not a variable name
Change all occurrances of Address as a variable name to instead use Addr.
Address is an allowed name in slicc even when Address is also being used as a
type, leading to declarations of "Address Address". While this works, it
prevents adding another field of type Address because the compiler then thinks
Address is a variable name, not type.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/mem/protocol/MI_example-cache.sm')
-rw-r--r-- | src/mem/protocol/MI_example-cache.sm | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index a0a23c308..d22a0d3e9 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -195,22 +195,22 @@ machine(L1Cache, "MI Example L1 Cache") in_port(forwardRequestNetwork_in, RequestMsg, forwardToCache) { if (forwardRequestNetwork_in.isReady()) { - peek(forwardRequestNetwork_in, RequestMsg, block_on="Address") { + peek(forwardRequestNetwork_in, RequestMsg, block_on="Addr") { - Entry cache_entry := getCacheEntry(in_msg.Address); - TBE tbe := TBEs[in_msg.Address]; + Entry cache_entry := getCacheEntry(in_msg.Addr); + TBE tbe := TBEs[in_msg.Addr]; if (in_msg.Type == CoherenceRequestType:GETX) { - trigger(Event:Fwd_GETX, in_msg.Address, cache_entry, tbe); + trigger(Event:Fwd_GETX, in_msg.Addr, cache_entry, tbe); } else if (in_msg.Type == CoherenceRequestType:WB_ACK) { - trigger(Event:Writeback_Ack, in_msg.Address, cache_entry, tbe); + trigger(Event:Writeback_Ack, in_msg.Addr, cache_entry, tbe); } else if (in_msg.Type == CoherenceRequestType:WB_NACK) { - trigger(Event:Writeback_Nack, in_msg.Address, cache_entry, tbe); + trigger(Event:Writeback_Nack, in_msg.Addr, cache_entry, tbe); } else if (in_msg.Type == CoherenceRequestType:INV) { - trigger(Event:Inv, in_msg.Address, cache_entry, tbe); + trigger(Event:Inv, in_msg.Addr, cache_entry, tbe); } else { error("Unexpected message"); @@ -221,13 +221,13 @@ machine(L1Cache, "MI Example L1 Cache") in_port(responseNetwork_in, ResponseMsg, responseToCache) { if (responseNetwork_in.isReady()) { - peek(responseNetwork_in, ResponseMsg, block_on="Address") { + peek(responseNetwork_in, ResponseMsg, block_on="Addr") { - Entry cache_entry := getCacheEntry(in_msg.Address); - TBE tbe := TBEs[in_msg.Address]; + Entry cache_entry := getCacheEntry(in_msg.Addr); + TBE tbe := TBEs[in_msg.Addr]; if (in_msg.Type == CoherenceResponseType:DATA) { - trigger(Event:Data, in_msg.Address, cache_entry, tbe); + trigger(Event:Data, in_msg.Addr, cache_entry, tbe); } else { error("Unexpected message"); @@ -261,7 +261,7 @@ machine(L1Cache, "MI Example L1 Cache") action(a_issueRequest, "a", desc="Issue a request") { enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -272,7 +272,7 @@ machine(L1Cache, "MI Example L1 Cache") action(b_issuePUT, "b", desc="Issue a PUT request") { enqueue(requestNetwork_out, RequestMsg, latency=issue_latency) { assert(is_valid(cache_entry)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceRequestType:PUTX; out_msg.Requestor := machineID; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -285,7 +285,7 @@ machine(L1Cache, "MI Example L1 Cache") peek(forwardRequestNetwork_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(cache_entry)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); @@ -299,7 +299,7 @@ machine(L1Cache, "MI Example L1 Cache") peek(forwardRequestNetwork_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=cache_response_latency) { assert(is_valid(tbe)); - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; out_msg.Destination.add(in_msg.Requestor); |