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authorNilay Vaish <nilay@cs.wisc.edu>2014-11-06 05:42:20 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2014-11-06 05:42:20 -0600
commitd25b722e4a9500f2d4b2ca937900bf093242ddfa (patch)
tree8eaa415786c9f2ac2ffff67799068381fdbaf90f /src/mem/protocol/MI_example-cache.sm
parent0baaed60ab961b8eb3399ee2c34adeea7335f5b3 (diff)
downloadgem5-d25b722e4a9500f2d4b2ca937900bf093242ddfa.tar.xz
ruby: coherence protocols: remove data block from dirctory entry
This patch removes the data block present in the directory entry structure of each protocol in gem5's mainline. Firstly, this is required for moving towards common set of memory controllers for classic and ruby memory systems. Secondly, the data block was being misused in several places. It was being used for having free access to the physical memory instead of calling on the memory controller. From now on, the directory controller will not have a direct visibility into the physical memory. The Memory Vector object now resides in the Memory Controller class. This also means that some significant changes are being made to the functional accesses in ruby.
Diffstat (limited to 'src/mem/protocol/MI_example-cache.sm')
-rw-r--r--src/mem/protocol/MI_example-cache.sm21
1 files changed, 18 insertions, 3 deletions
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index ee774f4c2..b0217ffea 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -171,13 +171,28 @@ machine(L1Cache, "MI Example L1 Cache")
}
}
- DataBlock getDataBlock(Address addr), return_by_ref="yes" {
+ void functionalRead(Address addr, Packet *pkt) {
TBE tbe := TBEs[addr];
if(is_valid(tbe)) {
- return tbe.DataBlk;
+ testAndRead(addr, tbe.DataBlk, pkt);
+ } else {
+ testAndRead(addr, getCacheEntry(addr).DataBlk, pkt);
+ }
+ }
+
+ int functionalWrite(Address addr, Packet *pkt) {
+ int num_functional_writes := 0;
+
+ TBE tbe := TBEs[addr];
+ if(is_valid(tbe)) {
+ num_functional_writes := num_functional_writes +
+ testAndWrite(addr, tbe.DataBlk, pkt);
+ return num_functional_writes;
}
- return getCacheEntry(addr).DataBlk;
+ num_functional_writes := num_functional_writes +
+ testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt);
+ return num_functional_writes;
}
// NETWORK PORTS