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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-19 10:02:01 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-19 10:02:01 -0500 |
commit | 2f44dada688ace9c24f085a8422b3054c3edb72e (patch) | |
tree | 372bb043430552b0f4424eaa5571933883fcaaae /src/mem/protocol/MI_example-cache.sm | |
parent | 2d9f3f8582e2de60850852c803a8c8ba0d6b91b5 (diff) | |
download | gem5-2f44dada688ace9c24f085a8422b3054c3edb72e.tar.xz |
ruby: reverts to changeset: bf82f1f7b040
Diffstat (limited to 'src/mem/protocol/MI_example-cache.sm')
-rw-r--r-- | src/mem/protocol/MI_example-cache.sm | 20 |
1 files changed, 8 insertions, 12 deletions
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm index d247ce663..3380cd7e6 100644 --- a/src/mem/protocol/MI_example-cache.sm +++ b/src/mem/protocol/MI_example-cache.sm @@ -152,7 +152,7 @@ machine(L1Cache, "MI Example L1 Cache") } AccessPermission getAccessPermission(Addr addr) { - TBE tbe := TBEs.lookup(addr); + TBE tbe := TBEs[addr]; if(is_valid(tbe)) { return L1Cache_State_to_permission(tbe.TBEState); } @@ -172,7 +172,7 @@ machine(L1Cache, "MI Example L1 Cache") } void functionalRead(Addr addr, Packet *pkt) { - TBE tbe := TBEs.lookup(addr); + TBE tbe := TBEs[addr]; if(is_valid(tbe)) { testAndRead(addr, tbe.DataBlk, pkt); } else { @@ -183,7 +183,7 @@ machine(L1Cache, "MI Example L1 Cache") int functionalWrite(Addr addr, Packet *pkt) { int num_functional_writes := 0; - TBE tbe := TBEs.lookup(addr); + TBE tbe := TBEs[addr]; if(is_valid(tbe)) { num_functional_writes := num_functional_writes + testAndWrite(addr, tbe.DataBlk, pkt); @@ -205,7 +205,7 @@ machine(L1Cache, "MI Example L1 Cache") peek(forwardRequestNetwork_in, RequestMsg, block_on="addr") { Entry cache_entry := getCacheEntry(in_msg.addr); - TBE tbe := TBEs.lookup(in_msg.addr); + TBE tbe := TBEs[in_msg.addr]; if (in_msg.Type == CoherenceRequestType:GETX) { trigger(Event:Fwd_GETX, in_msg.addr, cache_entry, tbe); @@ -231,7 +231,7 @@ machine(L1Cache, "MI Example L1 Cache") peek(responseNetwork_in, ResponseMsg, block_on="addr") { Entry cache_entry := getCacheEntry(in_msg.addr); - TBE tbe := TBEs.lookup(in_msg.addr); + TBE tbe := TBEs[in_msg.addr]; if (in_msg.Type == CoherenceResponseType:DATA) { trigger(Event:Data, in_msg.addr, cache_entry, tbe); @@ -254,11 +254,11 @@ machine(L1Cache, "MI Example L1 Cache") // make room for the block trigger(Event:Replacement, cacheMemory.cacheProbe(in_msg.LineAddress), getCacheEntry(cacheMemory.cacheProbe(in_msg.LineAddress)), - TBEs.lookup(cacheMemory.cacheProbe(in_msg.LineAddress))); + TBEs[cacheMemory.cacheProbe(in_msg.LineAddress)]); } else { trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, - cache_entry, TBEs.lookup(in_msg.LineAddress)); + cache_entry, TBEs[in_msg.LineAddress]); } } } @@ -353,7 +353,6 @@ machine(L1Cache, "MI Example L1 Cache") action(r_load_hit, "r", desc="Notify sequencer the load completed.") { assert(is_valid(cache_entry)); DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk); - cacheMemory.setMRU(cache_entry); sequencer.readCallback(address, cache_entry.DataBlk, false); } @@ -361,7 +360,6 @@ machine(L1Cache, "MI Example L1 Cache") peek(responseNetwork_in, ResponseMsg) { assert(is_valid(cache_entry)); DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk); - cacheMemory.setMRU(cache_entry); sequencer.readCallback(address, cache_entry.DataBlk, true, machineIDToMachineType(in_msg.Sender)); } @@ -370,7 +368,6 @@ machine(L1Cache, "MI Example L1 Cache") action(s_store_hit, "s", desc="Notify sequencer that store completed.") { assert(is_valid(cache_entry)); DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk); - cacheMemory.setMRU(cache_entry); sequencer.writeCallback(address, cache_entry.DataBlk, false); } @@ -378,7 +375,6 @@ machine(L1Cache, "MI Example L1 Cache") peek(responseNetwork_in, ResponseMsg) { assert(is_valid(cache_entry)); DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk); - cacheMemory.setMRU(cache_entry); sequencer.writeCallback(address, cache_entry.DataBlk, true, machineIDToMachineType(in_msg.Sender)); } @@ -400,7 +396,7 @@ machine(L1Cache, "MI Example L1 Cache") action(v_allocateTBE, "v", desc="Allocate TBE") { TBEs.allocate(address); - set_tbe(TBEs.lookup(address)); + set_tbe(TBEs[address]); } action(w_deallocateTBE, "w", desc="Deallocate TBE") { |