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authorTony Gutierrez <anthony.gutierrez@amd.com>2015-07-20 09:15:18 -0500
committerTony Gutierrez <anthony.gutierrez@amd.com>2015-07-20 09:15:18 -0500
commita3177645773b8eb4b835050c395554d3e2b4664a (patch)
tree793299969de1562785063448ac12f9e06ac164e3 /src/mem/protocol/MI_example-cache.sm
parent3f68884c0e432cdc241ed0442e19ade0d74aa6f4 (diff)
downloadgem5-a3177645773b8eb4b835050c395554d3e2b4664a.tar.xz
ruby: slicc: have a static MachineType
This patch is imported from reviewboard patch 2551 by Nilay. This patch moves from a dynamically defined MachineType to a statically defined one. The need for this patch was felt since a dynamically defined type prevents us from having types for which no machine definition may exist. The following changes have been made: i. each machine definition now uses a type from the MachineType enumeration instead of any random identifier. This required changing the grammar and the *.sm files. ii. MachineType enumeration defined statically in RubySlicc_Exports.sm. * * * normal protocol fixes for nilay's parser machine type fix
Diffstat (limited to 'src/mem/protocol/MI_example-cache.sm')
-rw-r--r--src/mem/protocol/MI_example-cache.sm2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index 1a83704e2..0e3e6e1eb 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -27,7 +27,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-machine(L1Cache, "MI Example L1 Cache")
+machine(MachineType:L1Cache, "MI Example L1 Cache")
: Sequencer * sequencer;
CacheMemory * cacheMemory;
Cycles cache_response_latency := 12;