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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:49 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:49 -0400 |
| commit | aa329f4757639820f921bf4152c21e79da74c034 (patch) | |
| tree | 8b0feb741790f9339e2c4dda97c551592a42fa60 /src/mem/protocol/MI_example-cache.sm | |
| parent | 64806c4c13040832dd1e24b8fb0c347cd794398e (diff) | |
| download | gem5-aa329f4757639820f921bf4152c21e79da74c034.tar.xz | |
config: Bump DRAM sweep bus speed to match DDR4 config
This patch bumps the bus clock speed such that the interconnect does
not become a bottleneck with a DDR4-2400-x64 DRAM delivering 19.2
GByte/s theoretical max.
Diffstat (limited to 'src/mem/protocol/MI_example-cache.sm')
0 files changed, 0 insertions, 0 deletions