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author | Derek Hower <drh5@cs.wisc.edu> | 2009-07-18 17:03:51 -0500 |
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committer | Derek Hower <drh5@cs.wisc.edu> | 2009-07-18 17:03:51 -0500 |
commit | 4b7ea4cb510465bc82c6679407d5a125cfddd18c (patch) | |
tree | ec7326aaf03b1a564acf3b4e83d27f488027b841 /src/mem/protocol/MI_example-dma.sm | |
parent | 340845b13989d4823a524521f0345ecb32f10894 (diff) | |
download | gem5-4b7ea4cb510465bc82c6679407d5a125cfddd18c.tar.xz |
ruby: fixed dma sequencer bug
The DMASequencer was still using a parameter from the old RubyConfig,
causing an offset error when the requested data wasn't block aligned.
This changeset also includes a fix to MI_example for a similar bug.
Diffstat (limited to 'src/mem/protocol/MI_example-dma.sm')
-rw-r--r-- | src/mem/protocol/MI_example-dma.sm | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm index 1f929cf9b..d5de18552 100644 --- a/src/mem/protocol/MI_example-dma.sm +++ b/src/mem/protocol/MI_example-dma.sm @@ -39,9 +39,9 @@ machine(DMA, "DMA Controller") { if (dmaRequestQueue_in.isReady()) { peek(dmaRequestQueue_in, DMARequestMsg) { if (in_msg.Type == DMARequestType:READ ) { - trigger(Event:ReadRequest, in_msg.PhysicalAddress); + trigger(Event:ReadRequest, in_msg.LineAddress); } else if (in_msg.Type == DMARequestType:WRITE) { - trigger(Event:WriteRequest, in_msg.PhysicalAddress); + trigger(Event:WriteRequest, in_msg.LineAddress); } else { error("Invalid request type"); } @@ -53,9 +53,9 @@ machine(DMA, "DMA Controller") { if (dmaResponseQueue_in.isReady()) { peek( dmaResponseQueue_in, DMAResponseMsg) { if (in_msg.Type == DMAResponseType:ACK) { - trigger(Event:Ack, in_msg.PhysicalAddress); + trigger(Event:Ack, in_msg.LineAddress); } else if (in_msg.Type == DMAResponseType:DATA) { - trigger(Event:Data, in_msg.PhysicalAddress); + trigger(Event:Data, in_msg.LineAddress); } else { error("Invalid response type"); } @@ -67,6 +67,7 @@ machine(DMA, "DMA Controller") { peek(dmaRequestQueue_in, DMARequestMsg) { enqueue(reqToDirectory_out, DMARequestMsg) { out_msg.PhysicalAddress := address; + out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:READ; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; @@ -80,6 +81,7 @@ machine(DMA, "DMA Controller") { peek(dmaRequestQueue_in, DMARequestMsg) { enqueue(reqToDirectory_out, DMARequestMsg) { out_msg.PhysicalAddress := address; + out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:WRITE; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; |