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| author | Joel Hestness <jthestness@gmail.com> | 2015-08-14 00:19:45 -0500 |
|---|---|---|
| committer | Joel Hestness <jthestness@gmail.com> | 2015-08-14 00:19:45 -0500 |
| commit | 905c0b347c785d07b606b6a9f3c6bbdf8ebe96a7 (patch) | |
| tree | e04c0fe6cf9ff037281e618a808bd390c6457f5b /src/mem/protocol/MI_example-dma.sm | |
| parent | 581bae9ecbafd5e94c5405ca925a55cc6e5d7488 (diff) | |
| download | gem5-905c0b347c785d07b606b6a9f3c6bbdf8ebe96a7.tar.xz | |
ruby: Protocol changes for SimObject MessageBuffers
Diffstat (limited to 'src/mem/protocol/MI_example-dma.sm')
| -rw-r--r-- | src/mem/protocol/MI_example-dma.sm | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm index c3cc29ba2..da6c5d926 100644 --- a/src/mem/protocol/MI_example-dma.sm +++ b/src/mem/protocol/MI_example-dma.sm @@ -32,9 +32,9 @@ machine(DMA, "DMA Controller") Cycles request_latency := 6; MessageBuffer * responseFromDir, network="From", virtual_network="1", - ordered="true", vnet_type="response"; + vnet_type="response"; MessageBuffer * requestToDir, network="To", virtual_network="0", - ordered="false", vnet_type="request"; + vnet_type="request"; { state_declaration(State, desc="DMA states", default="DMA_State_READY") { READY, AccessPermission:Invalid, desc="Ready to accept a new request"; @@ -49,7 +49,7 @@ machine(DMA, "DMA Controller") Ack, desc="DMA write to memory completed"; } - MessageBuffer mandatoryQueue, ordered="false"; + MessageBuffer mandatoryQueue; State cur_state; State getState(Address addr) { |