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authorBrad Beckmann <Brad.Beckmann@amd.com>2011-02-23 16:41:59 -0800
committerBrad Beckmann <Brad.Beckmann@amd.com>2011-02-23 16:41:59 -0800
commit12a05c23b7d351afee4b0c531021d8fb8ea5f57d (patch)
tree99a18647ecf642166068187915f2816a1007567d /src/mem/protocol/MOESI_CMP_directory-L1cache.sm
parent7842e955193c3fba850201acc45001306fe2ff9b (diff)
downloadgem5-12a05c23b7d351afee4b0c531021d8fb8ea5f57d.tar.xz
ruby: automate permission setting
This patch integrates permissions with cache and memory states, and then automates the setting of permissions within the generated code. No longer does one need to manually set the permissions within the setState funciton. This patch will faciliate easier functional access support by always correctly setting permissions for both cache and memory states. --HG-- rename : src/mem/slicc/ast/EnumDeclAST.py => src/mem/slicc/ast/StateDeclAST.py rename : src/mem/slicc/ast/TypeFieldEnumAST.py => src/mem/slicc/ast/TypeFieldStateAST.py
Diffstat (limited to 'src/mem/protocol/MOESI_CMP_directory-L1cache.sm')
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-L1cache.sm46
1 files changed, 16 insertions, 30 deletions
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
index e590c952a..50df2e52a 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -58,25 +58,25 @@ machine(L1Cache, "Directory protocol")
// STATES
- enumeration(State, desc="Cache states", default="L1Cache_State_I") {
+ state_declaration(State, desc="Cache states", default="L1Cache_State_I") {
// Base states
- I, desc="Idle";
- S, desc="Shared";
- O, desc="Owned";
- M, desc="Modified (dirty)";
- M_W, desc="Modified (dirty)";
- MM, desc="Modified (dirty and locally modified)";
- MM_W, desc="Modified (dirty and locally modified)";
+ I, AccessPermission:Invalid, desc="Idle";
+ S, AccessPermission:Read_Only, desc="Shared";
+ O, AccessPermission:Read_Only, desc="Owned";
+ M, AccessPermission:Read_Only, desc="Modified (dirty)";
+ M_W, AccessPermission:Read_Only, desc="Modified (dirty)";
+ MM, AccessPermission:Read_Write, desc="Modified (dirty and locally modified)";
+ MM_W, AccessPermission:Read_Write, desc="Modified (dirty and locally modified)";
// Transient States
- IM, "IM", desc="Issued GetX";
- SM, "SM", desc="Issued GetX, we still have an old copy of the line";
- OM, "SM", desc="Issued GetX, received data";
- IS, "IS", desc="Issued GetS";
- SI, "OI", desc="Issued PutS, waiting for ack";
- OI, "OI", desc="Issued PutO, waiting for ack";
- MI, "MI", desc="Issued PutX, waiting for ack";
- II, "II", desc="Issued PutX/O, saw Fwd_GETS or Fwd_GETX, waiting for ack";
+ IM, AccessPermission:Busy, "IM", desc="Issued GetX";
+ SM, AccessPermission:Read_Only, "SM", desc="Issued GetX, we still have an old copy of the line";
+ OM, AccessPermission:Read_Only, "SM", desc="Issued GetX, received data";
+ IS, AccessPermission:Busy, "IS", desc="Issued GetS";
+ SI, AccessPermission:Busy, "OI", desc="Issued PutS, waiting for ack";
+ OI, AccessPermission:Busy, "OI", desc="Issued PutO, waiting for ack";
+ MI, AccessPermission:Busy, "MI", desc="Issued PutX, waiting for ack";
+ II, AccessPermission:Busy, "II", desc="Issued PutX/O, saw Fwd_GETS or Fwd_GETX, waiting for ack";
}
// EVENTS
@@ -191,20 +191,6 @@ machine(L1Cache, "Directory protocol")
else {
cache_entry.CacheState := state;
}
-
- // Set permission
- if (state == State:MM || state == State:MM_W) {
- cache_entry.changePermission(AccessPermission:Read_Write);
- } else if ((state == State:S) ||
- (state == State:O) ||
- (state == State:M) ||
- (state == State:M_W) ||
- (state == State:SM) ||
- (state == State:OM)) {
- cache_entry.changePermission(AccessPermission:Read_Only);
- } else {
- cache_entry.changePermission(AccessPermission:Invalid);
- }
}
}