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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-02-10 21:26:24 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-02-10 21:26:24 -0600 |
commit | d3aebe1f91aa166329c8ee102fdcb2c9734fdceb (patch) | |
tree | f6f7807c24eccde98ee1e4bfe4c9c24b3c9392b2 /src/mem/protocol/MOESI_CMP_directory-L1cache.sm | |
parent | affd77ea77860fa9231aba8e43ad95dea06a114a (diff) | |
download | gem5-d3aebe1f91aa166329c8ee102fdcb2c9734fdceb.tar.xz |
ruby: replaces Time with Cycles in many places
The patch started of with replacing Time with Cycles in the Consumer class.
But to get ruby to compile, the rest of the changes had to be carried out.
Subsequent patches will further this process, till we completely replace
Time with Cycles.
Diffstat (limited to 'src/mem/protocol/MOESI_CMP_directory-L1cache.sm')
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index f6ed32009..101b7abd6 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -37,7 +37,8 @@ machine(L1Cache, "Directory protocol") CacheMemory * L1IcacheMemory, CacheMemory * L1DcacheMemory, int l2_select_num_bits, - int request_latency = 2, + Cycles request_latency = 2, + Cycles use_timeout_latency = 50, bool send_evictions { @@ -696,7 +697,7 @@ machine(L1Cache, "Directory protocol") } action(o_scheduleUseTimeout, "oo", desc="Schedule a use timeout.") { - useTimerTable.set(address, 50); + useTimerTable.set(address, use_timeout_latency); } action(ub_dmaUnblockL2Cache, "ub", desc="Send dma ack to l2 cache") { |