diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 12:04:47 -0500 |
---|---|---|
committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 12:04:47 -0500 |
commit | 9ea5d9cad9381e05004de28ef25309ebe94c3a79 (patch) | |
tree | 9e984df6ec20f479ea4c21fd29d1186052ef9ac0 /src/mem/protocol/MOESI_CMP_directory-L1cache.sm | |
parent | 93c173a95e985d6b1fd413a9cfb5a3f8839135c0 (diff) | |
download | gem5-9ea5d9cad9381e05004de28ef25309ebe94c3a79.tar.xz |
ruby: rename variables Addr to addr
Avoid clash between type Addr and variable name Addr.
Diffstat (limited to 'src/mem/protocol/MOESI_CMP_directory-L1cache.sm')
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-L1cache.sm | 98 |
1 files changed, 49 insertions, 49 deletions
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm index a8c9c5d1d..3543229d8 100644 --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm @@ -115,7 +115,7 @@ machine(L1Cache, "Directory protocol") // TBE fields structure(TBE, desc="...") { - Address Addr, desc="Physical address for this TBE"; + Address addr, desc="Physical address for this TBE"; State TBEState, desc="Transient state"; DataBlock DataBlk, desc="data for the block, required for concurrent writebacks"; bool Dirty, desc="Is the data dirty (different than memory)?"; @@ -278,8 +278,8 @@ machine(L1Cache, "Directory protocol") if (triggerQueue_in.isReady()) { peek(triggerQueue_in, TriggerMsg) { if (in_msg.Type == TriggerType:ALL_ACKS) { - trigger(Event:All_acks, in_msg.Addr, - getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]); + trigger(Event:All_acks, in_msg.addr, + getCacheEntry(in_msg.addr), TBEs[in_msg.addr]); } else { error("Unexpected message"); } @@ -292,36 +292,36 @@ machine(L1Cache, "Directory protocol") // Request Network in_port(requestNetwork_in, RequestMsg, requestToL1Cache) { if (requestNetwork_in.isReady()) { - peek(requestNetwork_in, RequestMsg, block_on="Addr") { + peek(requestNetwork_in, RequestMsg, block_on="addr") { assert(in_msg.Destination.isElement(machineID)); DPRINTF(RubySlicc, "L1 received: %s\n", in_msg.Type); if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:DMA_WRITE) { if (in_msg.Requestor == machineID && in_msg.RequestorMachine == MachineType:L1Cache) { - trigger(Event:Own_GETX, in_msg.Addr, - getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]); + trigger(Event:Own_GETX, in_msg.addr, + getCacheEntry(in_msg.addr), TBEs[in_msg.addr]); } else { - trigger(Event:Fwd_GETX, in_msg.Addr, - getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]); + trigger(Event:Fwd_GETX, in_msg.addr, + getCacheEntry(in_msg.addr), TBEs[in_msg.addr]); } } else if (in_msg.Type == CoherenceRequestType:GETS) { - trigger(Event:Fwd_GETS, in_msg.Addr, - getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]); + trigger(Event:Fwd_GETS, in_msg.addr, + getCacheEntry(in_msg.addr), TBEs[in_msg.addr]); } else if (in_msg.Type == CoherenceRequestType:DMA_READ) { - trigger(Event:Fwd_DMA, in_msg.Addr, - getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]); + trigger(Event:Fwd_DMA, in_msg.addr, + getCacheEntry(in_msg.addr), TBEs[in_msg.addr]); } else if (in_msg.Type == CoherenceRequestType:WB_ACK) { - trigger(Event:Writeback_Ack, in_msg.Addr, - getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]); + trigger(Event:Writeback_Ack, in_msg.addr, + getCacheEntry(in_msg.addr), TBEs[in_msg.addr]); } else if (in_msg.Type == CoherenceRequestType:WB_ACK_DATA) { - trigger(Event:Writeback_Ack_Data, in_msg.Addr, - getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]); + trigger(Event:Writeback_Ack_Data, in_msg.addr, + getCacheEntry(in_msg.addr), TBEs[in_msg.addr]); } else if (in_msg.Type == CoherenceRequestType:WB_NACK) { - trigger(Event:Writeback_Nack, in_msg.Addr, - getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]); + trigger(Event:Writeback_Nack, in_msg.addr, + getCacheEntry(in_msg.addr), TBEs[in_msg.addr]); } else if (in_msg.Type == CoherenceRequestType:INV) { - trigger(Event:Inv, in_msg.Addr, - getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]); + trigger(Event:Inv, in_msg.addr, + getCacheEntry(in_msg.addr), TBEs[in_msg.addr]); } else { error("Unexpected message"); } @@ -332,16 +332,16 @@ machine(L1Cache, "Directory protocol") // Response Network in_port(responseToL1Cache_in, ResponseMsg, responseToL1Cache) { if (responseToL1Cache_in.isReady()) { - peek(responseToL1Cache_in, ResponseMsg, block_on="Addr") { + peek(responseToL1Cache_in, ResponseMsg, block_on="addr") { if (in_msg.Type == CoherenceResponseType:ACK) { - trigger(Event:Ack, in_msg.Addr, - getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]); + trigger(Event:Ack, in_msg.addr, + getCacheEntry(in_msg.addr), TBEs[in_msg.addr]); } else if (in_msg.Type == CoherenceResponseType:DATA) { - trigger(Event:Data, in_msg.Addr, - getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]); + trigger(Event:Data, in_msg.addr, + getCacheEntry(in_msg.addr), TBEs[in_msg.addr]); } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) { - trigger(Event:Exclusive_Data, in_msg.Addr, - getCacheEntry(in_msg.Addr), TBEs[in_msg.Addr]); + trigger(Event:Exclusive_Data, in_msg.addr, + getCacheEntry(in_msg.addr), TBEs[in_msg.addr]); } else { error("Unexpected message"); } @@ -430,7 +430,7 @@ machine(L1Cache, "Directory protocol") action(a_issueGETS, "a", desc="Issue GETS") { peek(mandatoryQueue_in, RubyRequest) { enqueue(requestNetwork_out, RequestMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceRequestType:GETS; out_msg.Requestor := machineID; out_msg.RequestorMachine := MachineType:L1Cache; @@ -446,7 +446,7 @@ machine(L1Cache, "Directory protocol") action(b_issueGETX, "b", desc="Issue GETX") { peek(mandatoryQueue_in, RubyRequest) { enqueue(requestNetwork_out, RequestMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceRequestType:GETX; out_msg.Requestor := machineID; out_msg.RequestorMachine := MachineType:L1Cache; @@ -461,7 +461,7 @@ machine(L1Cache, "Directory protocol") action(d_issuePUTX, "d", desc="Issue PUTX") { enqueue(requestNetwork_out, RequestMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceRequestType:PUTX; out_msg.Requestor := machineID; out_msg.RequestorMachine := MachineType:L1Cache; @@ -473,7 +473,7 @@ machine(L1Cache, "Directory protocol") action(dd_issuePUTO, "\d", desc="Issue PUTO") { enqueue(requestNetwork_out, RequestMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceRequestType:PUTO; out_msg.Requestor := machineID; out_msg.RequestorMachine := MachineType:L1Cache; @@ -485,7 +485,7 @@ machine(L1Cache, "Directory protocol") action(dd_issuePUTS, "\ds", desc="Issue PUTS") { enqueue(requestNetwork_out, RequestMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceRequestType:PUTS; out_msg.Requestor := machineID; out_msg.RequestorMachine := MachineType:L1Cache; @@ -500,7 +500,7 @@ machine(L1Cache, "Directory protocol") assert(is_valid(cache_entry)); if (in_msg.RequestorMachine == MachineType:L2Cache) { enqueue(responseNetwork_out, ResponseMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; @@ -512,11 +512,11 @@ machine(L1Cache, "Directory protocol") out_msg.Acks := in_msg.Acks; out_msg.MessageSize := MessageSizeType:Response_Data; } - DPRINTF(RubySlicc, "Sending data to L2: %s\n", in_msg.Addr); + DPRINTF(RubySlicc, "Sending data to L2: %s\n", in_msg.addr); } else { enqueue(responseNetwork_out, ResponseMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; @@ -535,7 +535,7 @@ machine(L1Cache, "Directory protocol") action(e_sendDataToL2, "ee", desc="Send data from cache to requestor") { enqueue(responseNetwork_out, ResponseMsg, request_latency) { assert(is_valid(cache_entry)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; @@ -553,7 +553,7 @@ machine(L1Cache, "Directory protocol") assert(is_valid(cache_entry)); if (in_msg.RequestorMachine == MachineType:L2Cache) { enqueue(responseNetwork_out, ResponseMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; @@ -568,7 +568,7 @@ machine(L1Cache, "Directory protocol") } else { enqueue(responseNetwork_out, ResponseMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; @@ -587,7 +587,7 @@ machine(L1Cache, "Directory protocol") peek(requestNetwork_in, RequestMsg) { if (in_msg.RequestorMachine == MachineType:L1Cache) { enqueue(responseNetwork_out, ResponseMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; @@ -598,7 +598,7 @@ machine(L1Cache, "Directory protocol") } else { enqueue(responseNetwork_out, ResponseMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:ACK; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; @@ -613,7 +613,7 @@ machine(L1Cache, "Directory protocol") action(g_sendUnblock, "g", desc="Send unblock to memory") { enqueue(responseNetwork_out, ResponseMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; @@ -625,7 +625,7 @@ machine(L1Cache, "Directory protocol") action(gg_sendUnblockExclusive, "\g", desc="Send unblock exclusive to memory") { enqueue(responseNetwork_out, ResponseMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; @@ -709,7 +709,7 @@ machine(L1Cache, "Directory protocol") assert(is_valid(tbe)); if (tbe.NumPendingMsgs == 0) { enqueue(triggerQueue_out, TriggerMsg) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := TriggerType:ALL_ACKS; } } @@ -722,7 +722,7 @@ machine(L1Cache, "Directory protocol") action(ub_dmaUnblockL2Cache, "ub", desc="Send dma ack to l2 cache") { peek(requestNetwork_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DMA_ACK; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; @@ -741,7 +741,7 @@ machine(L1Cache, "Directory protocol") if (in_msg.RequestorMachine == MachineType:L1Cache || in_msg.RequestorMachine == MachineType:DMA) { enqueue(responseNetwork_out, ResponseMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; @@ -755,7 +755,7 @@ machine(L1Cache, "Directory protocol") } else { enqueue(responseNetwork_out, ResponseMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; @@ -776,7 +776,7 @@ machine(L1Cache, "Directory protocol") assert(is_valid(tbe)); if (in_msg.RequestorMachine == MachineType:L1Cache) { enqueue(responseNetwork_out, ResponseMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; @@ -789,7 +789,7 @@ machine(L1Cache, "Directory protocol") } else { enqueue(responseNetwork_out, ResponseMsg, request_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:DATA_EXCLUSIVE; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; @@ -808,7 +808,7 @@ machine(L1Cache, "Directory protocol") action(qq_sendWBDataFromTBEToL2, "\q", desc="Send data from TBE to L2") { enqueue(responseNetwork_out, ResponseMsg, request_latency) { assert(is_valid(tbe)); - out_msg.Addr := address; + out_msg.addr := address; out_msg.Sender := machineID; out_msg.SenderMachine := MachineType:L1Cache; out_msg.Destination.add(mapAddressToRange(address, MachineType:L2Cache, |