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authorBrad Beckmann <Brad.Beckmann@amd.com>2010-01-29 20:29:26 -0800
committerBrad Beckmann <Brad.Beckmann@amd.com>2010-01-29 20:29:26 -0800
commit31fcf09a68fd2aa680f1d1ce8c83ae9ad4407848 (patch)
tree5c10ec08e6b0ef739501f8f3cd146d2988896ee8 /src/mem/protocol/MOESI_CMP_directory-L1cache.sm
parent1c4405ad5eaa2733b677a194c2ea904d5a7ee269 (diff)
downloadgem5-31fcf09a68fd2aa680f1d1ce8c83ae9ad4407848.tar.xz
ruby: MOESI_CMP_directory updated to the new config system
Diffstat (limited to 'src/mem/protocol/MOESI_CMP_directory-L1cache.sm')
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-L1cache.sm26
1 files changed, 8 insertions, 18 deletions
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
index f6b1d4f38..3f9980d67 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -33,9 +33,11 @@
*/
machine(L1Cache, "Directory protocol")
- : int request_latency,
- int l2_select_low_bit,
- int l2_select_num_bits
+ : Sequencer * sequencer,
+ CacheMemory * L1IcacheMemory,
+ CacheMemory * L1DcacheMemory,
+ int l2_select_num_bits,
+ int request_latency = 2
{
// NODE L1 CACHE
@@ -127,16 +129,6 @@ machine(L1Cache, "Directory protocol")
int NumPendingMsgs, default="0", desc="Number of acks/data messages that this processor is waiting for";
}
- external_type(CacheMemory) {
- bool cacheAvail(Address);
- Address cacheProbe(Address);
- void allocate(Address, Entry);
- void deallocate(Address);
- Entry lookup(Address);
- void changePermission(Address, AccessPermission);
- bool isTagPresent(Address);
- }
-
external_type(TBETable) {
TBE lookup(Address);
void allocate(Address);
@@ -146,18 +138,16 @@ machine(L1Cache, "Directory protocol")
MessageBuffer mandatoryQueue, ordered="false", abstract_chip_ptr="true";
- Sequencer sequencer, factory='RubySystem::getSequencer(m_cfg["sequencer"])';
TBETable TBEs, template_hack="<L1Cache_TBE>";
- CacheMemory L1IcacheMemory, factory='RubySystem::getCache(m_cfg["icache"])';
- CacheMemory L1DcacheMemory, factory='RubySystem::getCache(m_cfg["dcache"])';
TimerTable useTimerTable;
+ int l2_select_low_bit, default="RubySystem::getBlockSizeBits()";
Entry getCacheEntry(Address addr), return_by_ref="yes" {
if (L1DcacheMemory.isTagPresent(addr)) {
- return L1DcacheMemory[addr];
+ return static_cast(Entry, L1DcacheMemory[addr]);
} else {
- return L1IcacheMemory[addr];
+ return static_cast(Entry, L1IcacheMemory[addr]);
}
}