diff options
author | Derek Hower <drh5@cs.wisc.edu> | 2009-08-06 03:41:28 -0500 |
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committer | Derek Hower <drh5@cs.wisc.edu> | 2009-08-06 03:41:28 -0500 |
commit | cbc52ef6c564837060a64ca33780af9152d8d38e (patch) | |
tree | 8e949e5284a021062fd3a419b60357f4c8554427 /src/mem/protocol/MOESI_CMP_directory-dma.sm | |
parent | f5e0c56da24ad1b6ee51592d19a9babb7b59da05 (diff) | |
download | gem5-cbc52ef6c564837060a64ca33780af9152d8d38e.tar.xz |
fixed MOESI_CMP_directory bug
Diffstat (limited to 'src/mem/protocol/MOESI_CMP_directory-dma.sm')
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-dma.sm | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm index da10695d0..ae86e24da 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -83,9 +83,9 @@ machine(DMA, "DMA Controller") if (dmaRequestQueue_in.isReady()) { peek(dmaRequestQueue_in, SequencerMsg) { if (in_msg.Type == SequencerRequestType:LD ) { - trigger(Event:ReadRequest, in_msg.PhysicalAddress); + trigger(Event:ReadRequest, in_msg.LineAddress); } else if (in_msg.Type == SequencerRequestType:ST) { - trigger(Event:WriteRequest, in_msg.PhysicalAddress); + trigger(Event:WriteRequest, in_msg.LineAddress); } else { error("Invalid request type"); } @@ -97,12 +97,12 @@ machine(DMA, "DMA Controller") if (dmaResponseQueue_in.isReady()) { peek( dmaResponseQueue_in, ResponseMsg) { if (in_msg.Type == CoherenceResponseType:DMA_ACK) { - trigger(Event:DMA_Ack, in_msg.Address); + trigger(Event:DMA_Ack, makeLineAddress(in_msg.Address)); } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE || in_msg.Type == CoherenceResponseType:DATA) { - trigger(Event:Data, in_msg.Address); + trigger(Event:Data, makeLineAddress(in_msg.Address)); } else if (in_msg.Type == CoherenceResponseType:ACK) { - trigger(Event:Inv_Ack, in_msg.Address); + trigger(Event:Inv_Ack, makeLineAddress(in_msg.Address)); } else { error("Invalid response type"); } @@ -126,7 +126,7 @@ machine(DMA, "DMA Controller") action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { - out_msg.Address := address; + out_msg.Address := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_READ; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; @@ -140,7 +140,7 @@ machine(DMA, "DMA Controller") action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { - out_msg.Address := address; + out_msg.Address := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_WRITE; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; |