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author | Lena Olson <lena@cs.wisc.edu> | 2013-06-18 16:58:33 -0500 |
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committer | Lena Olson <lena@cs.wisc.edu> | 2013-06-18 16:58:33 -0500 |
commit | 7c39d5df7ea61a39ad1b9a3aa70d22f0e2943b21 (patch) | |
tree | d2d2ca457dd5a1d43ee2389ce7202b68f567b951 /src/mem/protocol/MOESI_CMP_directory-dma.sm | |
parent | d06064c38613662dfbf68a701052278b4018de8c (diff) | |
download | gem5-7c39d5df7ea61a39ad1b9a3aa70d22f0e2943b21.tar.xz |
ruby: restrict Address to being a type and not a variable name
Change all occurrances of Address as a variable name to instead use Addr.
Address is an allowed name in slicc even when Address is also being used as a
type, leading to declarations of "Address Address". While this works, it
prevents adding another field of type Address because the compiler then thinks
Address is a variable name, not type.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Diffstat (limited to 'src/mem/protocol/MOESI_CMP_directory-dma.sm')
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-dma.sm | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm index d96276245..f79f0a535 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -120,15 +120,15 @@ machine(DMA, "DMA Controller") if (dmaResponseQueue_in.isReady()) { peek( dmaResponseQueue_in, ResponseMsg) { if (in_msg.Type == CoherenceResponseType:DMA_ACK) { - trigger(Event:DMA_Ack, makeLineAddress(in_msg.Address), - TBEs[makeLineAddress(in_msg.Address)]); + trigger(Event:DMA_Ack, makeLineAddress(in_msg.Addr), + TBEs[makeLineAddress(in_msg.Addr)]); } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE || in_msg.Type == CoherenceResponseType:DATA) { - trigger(Event:Data, makeLineAddress(in_msg.Address), - TBEs[makeLineAddress(in_msg.Address)]); + trigger(Event:Data, makeLineAddress(in_msg.Addr), + TBEs[makeLineAddress(in_msg.Addr)]); } else if (in_msg.Type == CoherenceResponseType:ACK) { - trigger(Event:Inv_Ack, makeLineAddress(in_msg.Address), - TBEs[makeLineAddress(in_msg.Address)]); + trigger(Event:Inv_Ack, makeLineAddress(in_msg.Addr), + TBEs[makeLineAddress(in_msg.Addr)]); } else { error("Invalid response type"); } @@ -141,7 +141,7 @@ machine(DMA, "DMA Controller") if (triggerQueue_in.isReady()) { peek(triggerQueue_in, TriggerMsg) { if (in_msg.Type == TriggerType:ALL_ACKS) { - trigger(Event:All_Acks, in_msg.Address, TBEs[in_msg.Address]); + trigger(Event:All_Acks, in_msg.Addr, TBEs[in_msg.Addr]); } else { error("Unexpected message"); } @@ -152,7 +152,7 @@ machine(DMA, "DMA Controller") action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { - out_msg.Address := in_msg.PhysicalAddress; + out_msg.Addr := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_READ; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; @@ -167,7 +167,7 @@ machine(DMA, "DMA Controller") action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { - out_msg.Address := in_msg.PhysicalAddress; + out_msg.Addr := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_WRITE; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; @@ -187,7 +187,7 @@ machine(DMA, "DMA Controller") assert(is_valid(tbe)); if (tbe.NumAcks == 0) { enqueue(triggerQueue_out, TriggerMsg) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := TriggerType:ALL_ACKS; } } @@ -202,7 +202,7 @@ machine(DMA, "DMA Controller") action( u_sendExclusiveUnblockToDir, "\u", desc="send exclusive unblock to directory") { enqueue(respToDirectory_out, ResponseMsg, latency=response_latency) { - out_msg.Address := address; + out_msg.Addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE; out_msg.Destination.add(map_Address_to_Directory(address)); out_msg.Sender := machineID; |