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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 12:04:47 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-08-14 12:04:47 -0500 |
commit | 9ea5d9cad9381e05004de28ef25309ebe94c3a79 (patch) | |
tree | 9e984df6ec20f479ea4c21fd29d1186052ef9ac0 /src/mem/protocol/MOESI_CMP_directory-dma.sm | |
parent | 93c173a95e985d6b1fd413a9cfb5a3f8839135c0 (diff) | |
download | gem5-9ea5d9cad9381e05004de28ef25309ebe94c3a79.tar.xz |
ruby: rename variables Addr to addr
Avoid clash between type Addr and variable name Addr.
Diffstat (limited to 'src/mem/protocol/MOESI_CMP_directory-dma.sm')
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-dma.sm | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm index 8aa7a5830..f534a0f62 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -123,15 +123,15 @@ machine(DMA, "DMA Controller") if (dmaResponseQueue_in.isReady()) { peek( dmaResponseQueue_in, ResponseMsg) { if (in_msg.Type == CoherenceResponseType:DMA_ACK) { - trigger(Event:DMA_Ack, makeLineAddress(in_msg.Addr), - TBEs[makeLineAddress(in_msg.Addr)]); + trigger(Event:DMA_Ack, makeLineAddress(in_msg.addr), + TBEs[makeLineAddress(in_msg.addr)]); } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE || in_msg.Type == CoherenceResponseType:DATA) { - trigger(Event:Data, makeLineAddress(in_msg.Addr), - TBEs[makeLineAddress(in_msg.Addr)]); + trigger(Event:Data, makeLineAddress(in_msg.addr), + TBEs[makeLineAddress(in_msg.addr)]); } else if (in_msg.Type == CoherenceResponseType:ACK) { - trigger(Event:Inv_Ack, makeLineAddress(in_msg.Addr), - TBEs[makeLineAddress(in_msg.Addr)]); + trigger(Event:Inv_Ack, makeLineAddress(in_msg.addr), + TBEs[makeLineAddress(in_msg.addr)]); } else { error("Invalid response type"); } @@ -144,7 +144,7 @@ machine(DMA, "DMA Controller") if (triggerQueue_in.isReady()) { peek(triggerQueue_in, TriggerMsg) { if (in_msg.Type == TriggerType:ALL_ACKS) { - trigger(Event:All_Acks, in_msg.Addr, TBEs[in_msg.Addr]); + trigger(Event:All_Acks, in_msg.addr, TBEs[in_msg.addr]); } else { error("Unexpected message"); } @@ -155,7 +155,7 @@ machine(DMA, "DMA Controller") action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { enqueue(reqToDirectory_out, RequestMsg, request_latency) { - out_msg.Addr := in_msg.PhysicalAddress; + out_msg.addr := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_READ; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; @@ -170,7 +170,7 @@ machine(DMA, "DMA Controller") action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { enqueue(reqToDirectory_out, RequestMsg, request_latency) { - out_msg.Addr := in_msg.PhysicalAddress; + out_msg.addr := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_WRITE; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; @@ -190,7 +190,7 @@ machine(DMA, "DMA Controller") assert(is_valid(tbe)); if (tbe.NumAcks == 0) { enqueue(triggerQueue_out, TriggerMsg) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := TriggerType:ALL_ACKS; } } @@ -205,7 +205,7 @@ machine(DMA, "DMA Controller") action( u_sendExclusiveUnblockToDir, "\u", desc="send exclusive unblock to directory") { enqueue(respToDirectory_out, ResponseMsg, response_latency) { - out_msg.Addr := address; + out_msg.addr := address; out_msg.Type := CoherenceResponseType:UNBLOCK_EXCLUSIVE; out_msg.Destination.add(map_Address_to_Directory(address)); out_msg.Sender := machineID; |