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authorNilay Vaish <nilay@cs.wisc.edu>2014-01-04 00:03:31 -0600
committerNilay Vaish <nilay@cs.wisc.edu>2014-01-04 00:03:31 -0600
commit5b1804e3bdb88aea7a198ff25617bb671cd34769 (patch)
tree38c8644bb17caaa708e6c678f0f495d7db5f74dc /src/mem/protocol/MOESI_CMP_token-L1cache.sm
parent9853ef6651e76883615595bf76f983ed43234f96 (diff)
downloadgem5-5b1804e3bdb88aea7a198ff25617bb671cd34769.tar.xz
ruby: add support for clusters
A cluster over here means a set of controllers that can be accessed only by a certain set of cores. For example, consider a two level hierarchy. Assume there are 4 L1 controllers (private) and 2 L2 controllers. We can have two different hierarchies here: a. the address space is partitioned between the two L2 controllers. Each L1 controller accesses both the L2 controllers. In this case, each L1 controller is a cluster initself. b. both the L2 controllers can cache any address. An L1 controller has access to only one of the L2 controllers. In this case, each L2 controller along with the L1 controllers that access it, form a cluster. This patch allows for each controller to have a cluster ID, which is 0 by default. By setting the cluster ID properly, one can instantiate hierarchies with clusters. Note that the coherence protocol might have to be changed as well.
Diffstat (limited to 'src/mem/protocol/MOESI_CMP_token-L1cache.sm')
-rw-r--r--src/mem/protocol/MOESI_CMP_token-L1cache.sm53
1 files changed, 21 insertions, 32 deletions
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
index e472d0437..463ecf65f 100644
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -406,7 +406,7 @@ machine(L1Cache, "Token protocol")
} else if (machineIDToMachineType(sender) == MachineType:L2Cache) {
if (sender == mapAddressToRange(addr, MachineType:L2Cache,
- l2_select_low_bit, l2_select_num_bits)) {
+ l2_select_low_bit, l2_select_num_bits, intToID(0))) {
return false;
} else {
return true;
@@ -540,9 +540,8 @@ machine(L1Cache, "Token protocol")
if ( machineIDToMachineType(in_msg.Sender) == MachineType:L2Cache ) {
if (in_msg.Sender == mapAddressToRange(in_msg.Addr,
- MachineType:L2Cache,
- l2_select_low_bit,
- l2_select_num_bits)) {
+ MachineType:L2Cache, l2_select_low_bit,
+ l2_select_num_bits, intToID(0))) {
// came from an off-chip L2 cache
if (is_valid(tbe)) {
@@ -748,9 +747,8 @@ machine(L1Cache, "Token protocol")
//out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
out_msg.Destination.add(mapAddressToRange(address,
- MachineType:L2Cache,
- l2_select_low_bit,
- l2_select_num_bits));
+ MachineType:L2Cache, l2_select_low_bit,
+ l2_select_num_bits, intToID(0)));
out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.MessageSize := MessageSizeType:Persistent_Control;
@@ -792,9 +790,8 @@ machine(L1Cache, "Token protocol")
out_msg.Type := CoherenceRequestType:GETS;
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address,
- MachineType:L2Cache,
- l2_select_low_bit,
- l2_select_num_bits));
+ MachineType:L2Cache, l2_select_low_bit,
+ l2_select_num_bits, intToID(0)));
out_msg.RetryNum := tbe.IssueCount;
if (tbe.IssueCount == 0) {
@@ -869,9 +866,8 @@ machine(L1Cache, "Token protocol")
//out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
out_msg.Destination.add(mapAddressToRange(address,
- MachineType:L2Cache,
- l2_select_low_bit,
- l2_select_num_bits));
+ MachineType:L2Cache, l2_select_low_bit,
+ l2_select_num_bits, intToID(0)));
out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.MessageSize := MessageSizeType:Persistent_Control;
@@ -914,9 +910,8 @@ machine(L1Cache, "Token protocol")
out_msg.Requestor := machineID;
out_msg.Destination.add(mapAddressToRange(address,
- MachineType:L2Cache,
- l2_select_low_bit,
- l2_select_num_bits));
+ MachineType:L2Cache, l2_select_low_bit,
+ l2_select_num_bits, intToID(0)));
out_msg.RetryNum := tbe.IssueCount;
@@ -991,9 +986,8 @@ machine(L1Cache, "Token protocol")
out_msg.Sender := machineID;
out_msg.Destination.add(mapAddressToRange(address,
- MachineType:L2Cache,
- l2_select_low_bit,
- l2_select_num_bits));
+ MachineType:L2Cache, l2_select_low_bit,
+ l2_select_num_bits, intToID(0)));
out_msg.Tokens := cache_entry.Tokens;
out_msg.DataBlk := cache_entry.DataBlk;
@@ -1016,9 +1010,8 @@ machine(L1Cache, "Token protocol")
out_msg.Sender := machineID;
out_msg.Destination.add(mapAddressToRange(address,
- MachineType:L2Cache,
- l2_select_low_bit,
- l2_select_num_bits));
+ MachineType:L2Cache, l2_select_low_bit,
+ l2_select_num_bits, intToID(0)));
out_msg.Tokens := cache_entry.Tokens;
out_msg.DataBlk := cache_entry.DataBlk;
@@ -1039,9 +1032,8 @@ machine(L1Cache, "Token protocol")
out_msg.Sender := machineID;
out_msg.Destination.add(mapAddressToRange(address,
- MachineType:L2Cache,
- l2_select_low_bit,
- l2_select_num_bits));
+ MachineType:L2Cache, l2_select_low_bit,
+ l2_select_num_bits, intToID(0)));
out_msg.Tokens := cache_entry.Tokens;
out_msg.DataBlk := cache_entry.DataBlk;
@@ -1384,10 +1376,8 @@ machine(L1Cache, "Token protocol")
out_msg.Sender := machineID;
out_msg.Destination.add(mapAddressToRange(address,
- MachineType:L2Cache,
- l2_select_low_bit,
- l2_select_num_bits));
-
+ MachineType:L2Cache, l2_select_low_bit,
+ l2_select_num_bits, intToID(0)));
out_msg.MessageSize := MessageSizeType:Response_Control;
}
}
@@ -1427,9 +1417,8 @@ machine(L1Cache, "Token protocol")
//out_msg.Destination.addNetDest(getAllPertinentL2Banks(address));
out_msg.Destination.add(mapAddressToRange(address,
- MachineType:L2Cache,
- l2_select_low_bit,
- l2_select_num_bits));
+ MachineType:L2Cache, l2_select_low_bit,
+ l2_select_num_bits, intToID(0)));
out_msg.Destination.add(map_Address_to_Directory(address));
out_msg.MessageSize := MessageSizeType:Persistent_Control;