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| author | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:46:12 -0700 |
|---|---|---|
| committer | Brad Beckmann <Brad.Beckmann@amd.com> | 2010-08-20 11:46:12 -0700 |
| commit | 29c45ccd2322470d0d6cef0ae20600c8c68f97e9 (patch) | |
| tree | ec62739567ba7d442c8b65550507cdab6b7827dc /src/mem/protocol/MOESI_CMP_token-L2cache.sm | |
| parent | 8e5c441a54b481085d6311f14af66e41b5766f91 (diff) | |
| download | gem5-29c45ccd2322470d0d6cef0ae20600c8c68f97e9.tar.xz | |
ruby: Reduced ruby latencies
The previous slower ruby latencies created a mismatch between the faster M5
cpu models and the much slower ruby memory system. Specifically smp
interrupts were much slower and infrequent, as well as cpus moving in and out
of spin locks. The result was many cpus were idle for large periods of time.
These changes fix the latency mismatch.
Diffstat (limited to 'src/mem/protocol/MOESI_CMP_token-L2cache.sm')
| -rw-r--r-- | src/mem/protocol/MOESI_CMP_token-L2cache.sm | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm index fcc91f223..a90b24800 100644 --- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm @@ -35,8 +35,8 @@ machine(L2Cache, "Token protocol") : CacheMemory * L2cacheMemory, int N_tokens, - int l2_request_latency = 10, - int l2_response_latency = 10, + int l2_request_latency = 5, + int l2_response_latency = 5, bool filtering_enabled = true { |