summaryrefslogtreecommitdiff
path: root/src/mem/protocol/MOESI_CMP_token-L2cache.sm
diff options
context:
space:
mode:
authorBrad Beckmann <Brad.Beckmann@amd.com>2010-01-29 20:29:25 -0800
committerBrad Beckmann <Brad.Beckmann@amd.com>2010-01-29 20:29:25 -0800
commitd77a9df3c10e528d206440f647ec975e9224c745 (patch)
treee662cfe98cf820312a58456073b669cc2b58d943 /src/mem/protocol/MOESI_CMP_token-L2cache.sm
parentd42152742ba245fd1c1611d4e7377cd31b84ed4a (diff)
downloadgem5-d77a9df3c10e528d206440f647ec975e9224c745.tar.xz
ruby: MOESI_CMP_token updates to use the new config system
Diffstat (limited to 'src/mem/protocol/MOESI_CMP_token-L2cache.sm')
-rw-r--r--src/mem/protocol/MOESI_CMP_token-L2cache.sm26
1 files changed, 7 insertions, 19 deletions
diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
index 9a5c400f2..fb50f6ca2 100644
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
@@ -33,10 +33,11 @@
*/
machine(L2Cache, "Token protocol")
- : int l2_request_latency,
- int l2_response_latency,
+ : CacheMemory * L2cacheMemory,
int N_tokens,
- bool filtering_enabled
+ int l2_request_latency = 10,
+ int l2_response_latency = 10,
+ bool filtering_enabled = true
{
// L2 BANK QUEUES
@@ -125,17 +126,6 @@ machine(L2Cache, "Token protocol")
bool exclusive, default="false", desc="if local exclusive is likely";
}
- external_type(CacheMemory) {
- bool cacheAvail(Address);
- Address cacheProbe(Address);
- void allocate(Address, Entry);
- void deallocate(Address);
- Entry lookup(Address);
- void changePermission(Address, AccessPermission);
- bool isTagPresent(Address);
- void setMRU(Address);
- }
-
external_type(PerfectCacheMemory) {
void allocate(Address);
void deallocate(Address);
@@ -154,22 +144,20 @@ machine(L2Cache, "Token protocol")
int countReadStarvingForAddress(Address);
}
- CacheMemory L2cacheMemory, factory='RubySystem::getCache(m_cfg["cache"])';
-
PersistentTable persistentTable;
PerfectCacheMemory localDirectory, template_hack="<L2Cache_DirEntry>";
Entry getL2CacheEntry(Address addr), return_by_ref="yes" {
if (L2cacheMemory.isTagPresent(addr)) {
- return L2cacheMemory[addr];
+ return static_cast(Entry, L2cacheMemory[addr]);
}
assert(false);
- return L2cacheMemory[addr];
+ return static_cast(Entry, L2cacheMemory[addr]);
}
int getTokens(Address addr) {
if (L2cacheMemory.isTagPresent(addr)) {
- return L2cacheMemory[addr].Tokens;
+ return getL2CacheEntry(addr).Tokens;
} else {
return 0;
}