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author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-05-21 11:32:24 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-05-21 11:32:24 -0500 |
commit | bd3d1955da7502187f732a3095ef27f2f95d4ff1 (patch) | |
tree | 35f092d8e452d7d1c79b0059d928e17b0410ba9a /src/mem/protocol/MOESI_CMP_token-dma.sm | |
parent | e7ce518168bea2e458ba654cf75d689d0d095ce7 (diff) | |
download | gem5-bd3d1955da7502187f732a3095ef27f2f95d4ff1.tar.xz |
ruby: moesi cmp token: cosmetic changes
Updates copyright years, removes space at the end of lines, shortens
variable names.
Diffstat (limited to 'src/mem/protocol/MOESI_CMP_token-dma.sm')
-rw-r--r-- | src/mem/protocol/MOESI_CMP_token-dma.sm | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm index 637778fcf..378344a09 100644 --- a/src/mem/protocol/MOESI_CMP_token-dma.sm +++ b/src/mem/protocol/MOESI_CMP_token-dma.sm @@ -27,7 +27,7 @@ */ -machine(DMA, "DMA Controller") +machine(DMA, "DMA Controller") : DMASequencer * dma_sequencer, Cycles request_latency = 6 { @@ -108,7 +108,7 @@ machine(DMA, "DMA Controller") peek(dmaRequestQueue_in, SequencerMsg) { enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) { out_msg.PhysicalAddress := in_msg.PhysicalAddress; - out_msg.LineAddress := in_msg.LineAddress; + out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:READ; out_msg.Requestor := machineID; out_msg.DataBlk := in_msg.DataBlk; @@ -123,7 +123,7 @@ machine(DMA, "DMA Controller") peek(dmaRequestQueue_in, SequencerMsg) { enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) { out_msg.PhysicalAddress := in_msg.PhysicalAddress; - out_msg.LineAddress := in_msg.LineAddress; + out_msg.LineAddress := in_msg.LineAddress; out_msg.Type := DMARequestType:WRITE; out_msg.Requestor := machineID; out_msg.DataBlk := in_msg.DataBlk; |