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authorNilay Vaish <nilay@cs.wisc.edu>2015-09-16 11:59:56 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-09-16 11:59:56 -0500
commitcd9e4458139658c4ce8f038e3a44bdecd17fa75d (patch)
treec7403c142a9bf36869f75016c683b9c7ef731399 /src/mem/protocol/MOESI_CMP_token-dma.sm
parent78a1245b4115373856514eacf2264141e6cd4aca (diff)
downloadgem5-cd9e4458139658c4ce8f038e3a44bdecd17fa75d.tar.xz
ruby: message buffer, timer table: significant changes
This patch changes MessageBuffer and TimerTable, two structures used for buffering messages by components in ruby. These structures would no longer maintain pointers to clock objects. Functions in these structures have been changed to take as input current time in Tick. Similarly, these structures will not operate on Cycle valued latencies for different operations. The corresponding functions would need to be provided with these latencies by components invoking the relevant functions. These latencies should also be in Ticks. I felt the need for these changes while trying to speed up ruby. The ultimate aim is to eliminate Consumer class and replace it with an EventManager object in the MessageBuffer and TimerTable classes. This object would be used for scheduling events. The event itself would contain information on the object and function to be invoked. In hindsight, it seems I should have done this while I was moving away from use of a single global clock in the memory system. That change led to introduction of clock objects that replaced the global clock object. It never crossed my mind that having clock object pointers is not a good design. And now I really don't like the fact that we have separate consumer, receiver and sender pointers in message buffers.
Diffstat (limited to 'src/mem/protocol/MOESI_CMP_token-dma.sm')
-rw-r--r--src/mem/protocol/MOESI_CMP_token-dma.sm10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm
index 4bb80d4ba..efe3db3cd 100644
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dma.sm
@@ -54,6 +54,8 @@ machine(DMA, "DMA Controller")
State cur_state;
+ Tick clockEdge();
+
State getState(Addr addr) {
return cur_state;
}
@@ -80,7 +82,7 @@ machine(DMA, "DMA Controller")
out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {
- if (dmaRequestQueue_in.isReady()) {
+ if (dmaRequestQueue_in.isReady(clockEdge())) {
peek(dmaRequestQueue_in, SequencerMsg) {
if (in_msg.Type == SequencerRequestType:LD ) {
trigger(Event:ReadRequest, in_msg.LineAddress);
@@ -94,7 +96,7 @@ machine(DMA, "DMA Controller")
}
in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") {
- if (dmaResponseQueue_in.isReady()) {
+ if (dmaResponseQueue_in.isReady(clockEdge())) {
peek( dmaResponseQueue_in, DMAResponseMsg) {
if (in_msg.Type == DMAResponseType:ACK) {
trigger(Event:Ack, in_msg.LineAddress);
@@ -150,11 +152,11 @@ machine(DMA, "DMA Controller")
}
action(p_popRequestQueue, "p", desc="Pop request queue") {
- dmaRequestQueue_in.dequeue();
+ dmaRequestQueue_in.dequeue(clockEdge());
}
action(p_popResponseQueue, "\p", desc="Pop request queue") {
- dmaResponseQueue_in.dequeue();
+ dmaResponseQueue_in.dequeue(clockEdge());
}
transition(READY, ReadRequest, BUSY_RD) {